100 Gb/s System Level Electrical Signaling Impact from EM Modal Artifacts in Hyperscale Networks

100 Gb/s System Level Electrical Signaling Impact from EM Modal Artifacts in Hyperscale Networks

应用文章

The paper will utilize the IEEE 802.3ck physical layer (PHY) specifications for 100 Gb/s per electrical lane signaling as a reference model to consider the system level impact of common-mode to differential-mode conversion and skew. Simulation models based on transmitter specifications such as signal-to-noise transmit (SNRTX), channel operating margin (COM), S-parameter models, and measurements of cable assemblies, backplanes, test fixtures, and channels will be presented to assess system impact.

The differential-mode insertion loss is an important element in the mixed mode scattering parameter matrix. It is used in deriving the Channel Operating Margin (COM), a figure of merit for a channel related to the ratio of a calculated signal amplitude to a calculated noise amplitude at a receiver input. The differential-mode insertion loss is derived from single-ended VNA measurements composed of four measurement terms representing the single-ended loss of each half of the differential-mode circuit as well as the single-ended conversion loss terms between each half of the differential-mode circuit.