Physical Layer Test System (PLTS) 2018

Data Collection & Analysis Software for Frequency and Time Domain Data with Optional Instrument Control

Includes What’s New in PLTS 2018 Software

Breakthrough spatial resolution of 6 picoseconds

The new Physical Layer Test System (PLTS) 2018 has significant breakthrough capabilities with regards to resolving adjacent impedance discontinuities within high-speed interconnects, such as cables, backplanes, PCBs and connectors. Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. PLTS 2018 now supports the new N5291A PNA MM-wave system that provides a single continuous sweep of 900 Hz to 120 GHz in a single box (see Figure 1 below). This new hardware support enables not only excellent low frequency performance for power integrity applications, but also achieves the best-in-class highest stop frequency of 120 GHz which directly translates to a 6-picosec­ond equivalent system risetime. This 6-picosecond risetime allows adjacent impedance discontinuities of less than 400 microns to be resolved in high-performance BGA (ball grid array) ceramic IC packages. High-speed SERDES chipsets designed for 400G network and data centers can now be fully characterized and optimized for high performance.

Python interface

Another significant enhancement to PLTS 2018 is the addition of a Python programming interface. Python is a widely used high-level programming language that features a dynamic system that supports multiple programming paradigms, includ­ing object-oriented, imperative, functional programming, and procedural styles. While the previous version of PLTS 2017 used the MATLAB programming interface, Python allows for custom processing of data out of and back into PLTS. This new language interface furthers the remote and factory automation applications for high-volume production of backplanes, PCBs, connectors, cables and IC packages. See the PLTS 2018 built-in Help for additional details and programming examples.

64-port S-parameter analysis

The last major enhancement to PLTS 2018 is 64-port S-param­eter capability. Many sophisticated backplane applications have multiple channels that need extensive crosstalk characterization in order to comply to the new high-speed digital standards. The 64-port S-parameter analysis allows eight differential pairs to be fully scrutinized for near-end and far-end crosstalk in any combination. This allows over 4096 waveforms to be recalled onto a PLTS canvas quickly and easily in multiple domains. There are very few signal integrity tools on the market that have a complete cross talk characterization of hardware and software built into a single analysis system.

Many other features not mentioned in this document can be found in PLTS 2018. Our design team looks forward to working together with you to overcome any signal integrity problems and help you design the highest quality data transmission channels possible.

Why is Physical Layer Testing Required?

The next generation computer and communication systems now being developed will handle data rates of multiple gigabits/second. Many systems will incorporate processors and SERDES chip sets that exceed GigaHertz clock frequen­cies. New and troubling input/output issues are emerging as switches, routers, server blades, and storage area networking equipment moving toward 100 Gbps data rates. Digital design engineers choosing chip-to-chip and backplane technologies for these systems are finding signal integrity challenges that have not been encountered before.

Traditional parallel bus topologies are running out of bandwidth. As parallel busses become wider, the complexity and cost to route on PC boards increase dramatically. The growing skew between data and clock lines has become increasingly difficult to resolve within parallel busses. The solution is fast serial channels. The newer serial bus structure is quickly replacing the parallel bus structure for high-speed digital systems. Engineers have been turning to a multitude of gigabit serial interconnect protocols with embedded clocking to achieve the goal of simple routing and more bandwidth per pin. However, these serial interconnects bring their own set of problems.

In order to maintain the same total bandwidth as the older parallel bus, the new serial bus needs to increase its data rate. As the data rate increases through serial interconnects, the rise time of the data transition from a zero logic level to a one logic level becomes shorter. This shorter rise time creates larger reflections at impedance discontinuities and degrade the eye diagram at the end of the channel. As a result, physical layer components such as printed circuit board traces, connectors, cables, and IC packages can no longer be ignored. In fact, in many cases, the silicon is so fast that the physical layer device has become the bottleneck.

In order to maintain signal integrity throughout the complete channel, engineers are moving away from single-ended circuits and now use differential circuits. The differential circuit pro­vides good Common Mode Rejection Ratio (CMRR) and helps shield adjacent PCB traces from crosstalk. Properly designed differential transmission lines will minimize the undesirable effect of mode conversion and enhance the maximum data rate throughput possible. Unfortunately, differential signaling technology is not always an intuitive science.

Differential transmission lines coupled with the microwave effects of high-speed data have created the need for new design and validation tools for the digital design engineer. Understanding the fundamental properties of signal propaga­tion through measurement and post-measurement analysis is mandatory for today’s leading edge telecommunication and computer systems. The traditional Time Domain Reflec­tometer (TDR) is still a very useful tool, but many times the Vector Network Analyzer (VNA) is needed for the complete characterization of physical layer components. There is a strong need for a test and measurement system that will allow simple characterization of complex microwave behavior seen in high speed digital interconnects. In fact, many digital standards groups have now recognized the importance of specifying frequency domain physical layer measurements as a compliance requirement. Many standards including Serial ATA and PCI Express® have adopted the SDD21 parameter (input differential insertion loss) as a required measurement to ensure channel compliance. This parameter is an indication of the frequency response that the differential signal sees as it propagates through the high-speed serial channel. An example of a proposed SDD21 compliance mask is shown in Figure 4 for the Channel Electrical Interface (CEI) working group for the Optical Internetworking Forum (OIF).