!!!! 6 0 1 974687438 V3079 ! Device : 74ls468 ! Function : Tri-state Octal Buffer ! revision : B.01.00 ! safeguard : standard_lsttl ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." combinatorial vector cycle 2u receive delay 1.9u assign VCC to pins 20 assign GND to pins 10 assign One_A_1 to pins 2 assign One_Y_1 to pins 3 assign One_A_2 to pins 4 assign One_Y_2 to pins 5 assign One_A_3 to pins 6 assign One_Y_3 to pins 7 assign One_A_4 to pins 8 assign One_Y_4 to pins 9 assign Two_A_1 to pins 12 assign Two_Y_1 to pins 11 assign Two_A_2 to pins 14 assign Two_Y_2 to pins 13 assign Two_A_3 to pins 16 assign Two_Y_3 to pins 15 assign Two_A_4 to pins 18 assign Two_Y_4 to pins 17 assign Low_enable_one to pins 1 assign Low_enable_two to pins 19 power VCC,GND family TTL inputs One_A_1,One_A_2,One_A_3,One_A_4,Two_A_1,Two_A_2,Two_A_3,Two_A_4 inputs Low_enable_one, Low_enable_two outputs One_Y_1,One_Y_2,One_Y_3,One_Y_4,Two_Y_1,Two_Y_2,Two_Y_3 outputs Two_Y_4 disable One_Y_1,One_Y_2,One_Y_3,One_Y_4 with Low_enable_one to "1" disable Two_Y_1,Two_Y_2,Two_Y_3,Two_Y_4 with Low_enable_two to "1" when Low_enable_one is "1" inactive One_Y_1, One_Y_2, One_Y_3, One_Y_4 when Low_enable_two is "1" inactive Two_Y_1,Two_Y_2,Two_Y_3,Two_Y_4 trace One_Y_1 to One_A_1, Low_enable_one trace One_Y_2 to One_A_2, Low_enable_one trace One_Y_3 to One_A_3, Low_enable_one trace One_Y_4 to One_A_4, Low_enable_one trace Two_Y_1 to Two_A_1, Low_enable_two trace Two_Y_2 to Two_A_2, Low_enable_two trace Two_Y_3 to Two_A_3, Low_enable_two trace Two_Y_4 to Two_A_4, Low_enable_two !******************************************************************************* !******************************************************************************* vector E1_high set Low_enable_one to "0" set One_A_1 to "1" set One_Y_1 to "0" end vector vector E1_low set Low_enable_one to "0" set One_A_1 to "0" set One_Y_1 to "1" end vector vector E2_high set Low_enable_one to "0" set One_A_2 to "1" set One_Y_2 to "0" end vector vector E2_low set Low_enable_one to "0" set One_A_2 to "0" set One_Y_2 to "1" end vector vector E3_high set Low_enable_one to "0" set One_A_3 to "1" set One_Y_3 to "0" end vector vector E3_low set Low_enable_one to "0" set One_A_3 to "0" set One_Y_3 to "1" end vector vector E4_high set Low_enable_one to "0" set One_A_4 to "1" set One_Y_4 to "0" end vector vector E4_low set Low_enable_one to "0" set One_A_4 to "0" set One_Y_4 to "1" end vector vector E5_high set Low_enable_two to "0" set Two_A_1 to "1" set Two_Y_1 to "0" end vector vector E5_low set Low_enable_two to "0" set Two_A_1 to "0" set Two_Y_1 to "1" end vector vector E6_high set Low_enable_two to "0" set Two_A_2 to "1" set Two_Y_2 to "0" end vector vector E6_low set Low_enable_two to "0" set Two_A_2 to "0" set Two_Y_2 to "1" end vector vector E7_high set Low_enable_two to "0" set Two_A_3 to "1" set Two_Y_3 to "0" end vector vector E7_low set Low_enable_two to "0" set Two_A_3 to "0" set Two_Y_3 to "1" end vector vector E8_high set Low_enable_two to "0" set Two_A_4 to "1" set Two_Y_4 to "0" end vector vector E8_low set Low_enable_two to "0" set Two_A_4 to "0" set Two_Y_4 to "1" end vector !*****VECTORS FOR DISABLE TESTS***** vector E1_low_Disabled set Low_enable_one to "1" set One_A_1 to "0" set One_Y_1 to "1" end vector vector E1_high_Disabled set Low_enable_one to "1" set One_A_1 to "1" set One_Y_1 to "0" end vector vector E2_low_Disabled set Low_enable_one to "1" set One_A_2 to "0" set One_Y_2 to "1" end vector vector E2_high_Disabled set Low_enable_one to "1" set One_A_2 to "1" set One_Y_2 to "0" end vector vector E3_low_Disabled set Low_enable_one to "1" set One_A_3 to "0" set One_Y_3 to "1" end vector vector E3_high_Disabled set Low_enable_one to "1" set One_A_3 to "1" set One_Y_3 to "0" end vector vector E4_low_Disabled set Low_enable_one to "1" set One_A_4 to "0" set One_Y_4 to "1" end vector vector E4_high_Disabled set Low_enable_one to "1" set One_A_4 to "1" set One_Y_4 to "0" end vector vector E5_low_Disabled set Low_enable_two to "1" set Two_A_1 to "0" set Two_Y_1 to "1" end vector vector E5_high_Disabled set Low_enable_two to "1" set Two_A_1 to "1" set Two_Y_1 to "0" end vector vector E6_low_Disabled set Low_enable_two to "1" set Two_A_2 to "0" set Two_Y_2 to "1" end vector vector E6_high_Disabled set Low_enable_two to "1" set Two_A_2 to "1" set Two_Y_2 to "0" end vector vector E7_low_Disabled set Low_enable_two to "1" set Two_A_3 to "0" set Two_Y_3 to "1" end vector vector E7_high_Disabled set Low_enable_two to "1" set Two_A_3 to "1" set Two_Y_3 to "0" end vector vector E8_low_Disabled set Low_enable_two to "1" set Two_A_4 to "0" set Two_Y_4 to "1" end vector vector E8_high_Disabled set Low_enable_two to "1" set Two_A_4 to "1" set Two_Y_4 to "0" end vector !******************************************************************************* unit "awaretest E1" !AT Modified the unit name execute E1_high execute E1_low end unit !AT Added a new "end unit" unit "awaretest E2" !AT Added this unit execute E2_high execute E2_low end unit !AT Added a new "end unit" unit "awaretest E3" !AT Added this unit execute E3_high execute E3_low end unit !AT Added a new "end unit" unit "awaretest E4" !AT Added this unit execute E4_high execute E4_low end unit !AT Added a new "end unit" unit "awaretest E5" !AT Added this unit execute E5_high execute E5_low end unit !AT Added a new "end unit" unit "awaretest E6" !AT Added this unit execute E6_high execute E6_low end unit !AT Added a new "end unit" unit "awaretest E7" !AT Added this unit execute E7_high execute E7_low end unit !AT Added a new "end unit" unit "awaretest E8" !AT Added this unit execute E8_high execute E8_low end unit !*****TESTS FOR DISABLE ************************** unit disable test "Disable test for Elements 1-4" execute E1_high_Disabled execute E1_low_Disabled execute E1_high_Disabled execute E2_high_Disabled execute E2_low_Disabled execute E2_high_Disabled execute E3_high_Disabled execute E3_low_Disabled execute E3_high_Disabled execute E4_high_Disabled execute E4_low_Disabled execute E4_high_Disabled end unit unit disable test "Disable test for Elements 5-8" execute E5_high_Disabled execute E5_low_Disabled execute E5_high_Disabled execute E6_high_Disabled execute E6_low_Disabled execute E6_high_Disabled execute E7_high_Disabled execute E7_low_Disabled execute E7_high_Disabled execute E8_high_Disabled execute E8_low_Disabled execute E8_high_Disabled end unit !END OF TEST!