!!!! 6 0 1 974690584 V96c0 ! Device : 8t37 ! Function : Bus Receiver ! revision : B.01.00 ! safeguard : standard_ttl ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." combinatorial vector cycle 500n receive delay 400n assign VCC to pins 16 assign GND to pins 8 assign In1 to pins 1 assign In3 to pins 3 assign In5 to pins 5 assign DisableA to pins 7 assign In11 to pins 11 assign In13 to pins 13 assign In15 to pins 15 assign DisableB to pins 9 assign Out2 to pins 2 assign Out4 to pins 4 assign Out6 to pins 6 assign Out10 to pins 10 assign Out12 to pins 12 assign Out14 to pins 14 family TTL power VCC,GND inputs In1, In3, In5, In11, In13, In15, DisableA, DisableB outputs Out2, Out4, Out6, Out10, Out12, Out14 trace Out2 to In1, DisableA trace Out4 to In3, DisableA trace Out6 to In5, DisableA trace Out10 to In11, DisableB trace Out12 to In13, DisableB trace Out14 to In15, DisableB !*************************************************************** !*************************************************************** vector In1_low set In1 to "0" set DisableA to "0" set Out2 to "1" end vector vector In1_high set In1 to "1" set DisableA to "0" set Out2 to "0" end vector vector In3_low set In3 to "0" set DisableA to "0" set Out4 to "1" end vector vector In3_high set In3 to "1" set DisableA to "0" set Out4 to "0" end vector vector In5_low set In5 to "0" set DisableA to "0" set Out6 to "1" end vector vector In5_high set In5 to "1" set DisableA to "0" set Out6 to "0" end vector vector In11_low set In11 to "0" set DisableB to "0" set Out10 to "1" end vector vector In11_high set In11 to "1" set DisableB to "0" set Out10 to "0" end vector vector In13_low set In13 to "0" set DisableB to "0" set Out12 to "1" end vector vector In13_high set In13 to "1" set DisableB to "0" set Out12 to "0" end vector vector In15_low set In15 to "0" set DisableB to "0" set Out14 to "1" end vector vector In15_high set In15 to "1" set DisableB to "0" set Out14 to "0" end vector vector DisableA_high set In5 to "0" set DisableA to "1" set Out6 to "0" end vector vector DisableB_high set In15 to "0" set DisableB to "1" set Out14 to "0" end vector !*************************************************************** !*************************************************************** !**************************************************************** unit "awaretest In1" !AT Modified the unit name execute In1_low execute In1_high end unit !AT Added a new "end unit" unit "awaretest In3" !AT Added this unit execute In3_low execute In3_high end unit !AT Added a new "end unit" unit "awaretest In5" !AT Added this unit execute In5_low execute In5_high end unit !AT Added a new "end unit" unit "awaretest In11" !AT Added this unit execute In11_low execute In11_high end unit !AT Added a new "end unit" unit "awaretest In13" !AT Added this unit execute In13_low execute In13_high end unit !AT Added a new "end unit" unit "awaretest In15" !AT Added this unit execute In15_low execute In15_high end unit !AT Added a new "end unit" unit "awaretest Disable" !AT Added this unit execute DisableA_high execute DisableB_high end unit !End of test