!!!!    6    0    1  974731261  Vad1c                                         

! Device           : 74hc242
! Function         : bus_transceiver 3-state inverting quad
! revision         : B.01.00
! safeguard        : high_out_hcmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

combinatorial

assign   VCC       to pins   14
assign   GND       to pins   7

assign   E1_A      to pins   3
assign   E1_B      to pins   11
assign   E2_A      to pins   4
assign   E2_B      to pins   10
assign   E3_A      to pins   5
assign   E3_B      to pins   9
assign   E4_A      to pins   6
assign   E4_B      to pins   8
assign   All_A     to pins   3,4,5,6
assign   All_B     to pins   11,10,9,8

assign   Enable_BA      to pins   13
assign   Enable_AB_bar  to pins   1
assign   Enables        to pins   13,1

assign   NC             to pins 2,12

family   CMOS

power    VCC, GND

inputs   Enable_BA, Enable_AB_bar, Enables
bidirectional  E1_A, E1_B, E2_A, E2_B, E3_A, E3_B, E4_A, E4_B
bidirectional  All_A, All_B

nondigital     NC

disable   All_A     with Enable_BA      to    "0"
disable   All_B     with Enable_AB_bar  to    "1"

when  Enable_BA     is "0" inputs    All_A
when  Enable_BA     is "0" outputs   All_B

when  Enable_AB_bar is "1" inputs    All_B
when  Enable_AB_bar is "1" outputs   All_A

trace E1_A to E1_B,Enables
trace E1_B to E1_A,Enables

trace E2_A to E2_B,Enables
trace E2_B to E2_A,Enables

trace E3_A to E3_B,Enables
trace E3_B to E3_A,Enables

trace E4_A to E4_B,Enables
trace E4_B to E4_A,Enables

!*********************************************************************
!*********************************************************************

vector  E1_A_hi
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E1_A           to "1"
   set   E1_B           to "0"
end vector

vector  E1_A_lo
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E1_A           to "0"
   set   E1_B           to "1"
end vector

vector  E2_A_hi
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E2_A           to "1"
   set   E2_B           to "0"
end vector

vector  E2_A_lo
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E2_A           to "0"
   set   E2_B           to "1"
end vector

vector  E3_A_hi
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E3_A           to "1"
   set   E3_B           to "0"
end vector

vector  E3_A_lo
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E3_A           to "0"
   set   E3_B           to "1"
end vector

vector  E4_A_hi
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E4_A           to "1"
   set   E4_B           to "0"
end vector

vector  E4_A_lo
   drive All_A
   receive  All_B
   set   Enables        to "00"
   set   E4_A           to "0"
   set   E4_B           to "1"
end vector

vector  E1_B_hi
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E1_B           to "1"
   set   E1_A           to "0"
end vector

vector  E1_B_lo
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E1_B           to "0"
   set   E1_A           to "1"
end vector

vector  E2_B_hi
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E2_B           to "1"
   set   E2_A           to "0"
end vector

vector  E2_B_lo
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E2_B           to "0"
   set   E2_A           to "1"
end vector

vector  E3_B_hi
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E3_B           to "1"
   set   E3_A           to "0"
end vector

vector  E3_B_lo
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E3_B           to "0"
   set   E3_A           to "1"
end vector

vector  E4_B_hi
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E4_B           to "1"
   set   E4_A           to "0"
end vector

vector  E4_B_lo
   drive All_B
   receive  All_A
   set   Enables        to "11"
   set   E4_B           to "0"
   set   E4_A           to "1"
end vector

!*****VECTORS FOR DISABLE TESTS*****

vector  E1_A_hi_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E1_A           to "1"
   set   E1_B           to "0"
end vector

vector  E1_A_lo_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E1_A           to "0"
   set   E1_B           to "1"
end vector

vector  E2_A_hi_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E2_A           to "1"
   set   E2_B           to "0"
end vector

vector  E2_A_lo_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E2_A           to "0"
   set   E2_B           to "1"
end vector

vector  E3_A_hi_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E3_A           to "1"
   set   E3_B           to "0"
end vector

vector  E3_A_lo_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E3_A           to "0"
   set   E3_B           to "1"
end vector

vector  E4_A_hi_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E4_A           to "1"
   set   E4_B           to "0"
end vector

vector  E4_A_lo_Disabled
   drive All_A
   receive  All_B
   set   Enables        to "11"
   set   E4_A           to "0"
   set   E4_B           to "1"
end vector

vector  E1_B_hi_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E1_B           to "1"
   set   E1_A           to "0"
end vector

vector  E1_B_lo_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E1_B           to "0"
   set   E1_A           to "1"
end vector

vector  E2_B_hi_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E2_B           to "1"
   set   E2_A           to "0"
end vector

vector  E2_B_lo_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E2_B           to "0"
   set   E2_A           to "1"
end vector

vector  E3_B_hi_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E3_B           to "1"
   set   E3_A           to "0"
end vector

vector  E3_B_lo_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E3_B           to "0"
   set   E3_A           to "1"
end vector

vector  E4_B_hi_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E4_B           to "1"
   set   E4_A           to "0"
end vector

vector  E4_B_lo_Disabled
   drive All_B
   receive  All_A
   set   Enables        to "00"
   set   E4_B           to "0"
   set   E4_A           to "1"
end vector

!*********************************************************************
!*********************************************************************

unit "awaretest E1 A in, B out"       !AT Modified the unit name
   execute  E1_A_lo
   execute  E1_A_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E2 A in, B out"       !AT Added this unit
   execute  E2_A_lo
   execute  E2_A_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E3 A in, B out"       !AT Added this unit
   execute  E3_A_lo
   execute  E3_A_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E4 A in, B out"       !AT Added this unit
   execute  E4_A_lo
   execute  E4_A_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E1 B in, A out"       !AT Modified the unit name
   execute  E1_B_lo
   execute  E1_B_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E2 B in, A out"       !AT Added this unit
   execute  E2_B_lo
   execute  E2_B_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E3 B in, A out"       !AT Added this unit
   execute  E3_B_lo
   execute  E3_B_hi
end unit                              !AT Added a new "end unit"

unit "awaretest E4 B in, A out"       !AT Added this unit
   execute  E4_B_lo
   execute  E4_B_hi
end unit                              !AT Added a new "end unit"

!*****TESTS FOR DISABLE **************************

unit  disable test "Disable Test for Output B"
   execute  E1_A_hi_Disabled
   execute  E1_A_lo_Disabled
   execute  E1_A_hi_Disabled
   execute  E2_A_hi_Disabled
   execute  E2_A_lo_Disabled
   execute  E2_A_hi_Disabled
   execute  E3_A_hi_Disabled
   execute  E3_A_lo_Disabled
   execute  E3_A_hi_Disabled
   execute  E4_A_hi_Disabled
   execute  E4_A_lo_Disabled
   execute  E4_A_hi_Disabled
end unit

unit  disable test "Disable Test for Output A"
   execute  E1_B_hi_Disabled
   execute  E1_B_lo_Disabled
   execute  E1_B_hi_Disabled
   execute  E2_B_hi_Disabled
   execute  E2_B_lo_Disabled
   execute  E2_B_hi_Disabled
   execute  E3_B_hi_Disabled
   execute  E3_B_lo_Disabled
   execute  E3_B_hi_Disabled
   execute  E4_B_hi_Disabled
   execute  E4_B_lo_Disabled
   execute  E4_B_hi_Disabled
end unit

!    End of test