!!!!    6    0    1  991863050  Vcab8                                         

! Device           : 4517
! Function         : Shift_Register 3_State 64_Bit
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : No modifications. This test is compatible for AwareTest xi
!

warning "Library/cmos/4517: This test is for a CMOS shift register."
warning "The '4517' 16k x 1 dynamic RAM is entered as 'MCM4517'"
!
! This test is a duplicate of 'library/cmos/4517b' with the above warning
! added.  Any changes to the test must be made in both library files.

sequential

vector cycle 1u
receive delay 900n

assign VDD to pins 16
assign VSS to pins 8

assign E1_Clock to pins 4
assign E1_Data to pins 7
assign E1_Write_Enable to pins 3
assign E1_Q_16 to pins 1
assign E1_Q_32 to pins 6
assign E1_Q_48 to pins 2
assign E1_Q_64 to pins 5

assign E2_Clock to pins 12
assign E2_Data to pins 9
assign E2_Write_Enable to pins 13
assign E2_Q_16 to pins 15
assign E2_Q_32 to pins 10
assign E2_Q_48 to pins 14
assign E2_Q_64 to pins 11

power  VDD,  VSS
family  CMOS

inputs E1_Clock, E1_Data, E1_Write_Enable
inputs E2_Clock, E2_Data, E2_Write_Enable


bidirectional E1_Q_16, E1_Q_32, E1_Q_48, E1_Q_64
bidirectional E2_Q_16, E2_Q_32, E2_Q_48, E2_Q_64

disable E1_Q_16    with E1_Write_Enable  to "1"
disable E2_Q_16    with E2_Write_Enable  to "1"
disable E1_Q_32    with E1_Write_Enable  to "1"
disable E2_Q_32    with E2_Write_Enable  to "1"
disable E1_Q_48    with E1_Write_Enable  to "1"
disable E2_Q_48    with E2_Write_Enable  to "1"
disable E1_Q_64    with E1_Write_Enable  to "1"
disable E2_Q_64    with E2_Write_Enable  to "1"

when  E2_Write_Enable  is "1"  inactive E2_Q_64
when  E1_Write_Enable  is "1"  inactive E1_Q_64

when  E1_Write_Enable  is "1"  inputs E1_Q_16
when  E1_Write_Enable  is "1"  inputs E1_Q_32
when  E1_Write_Enable  is "1"  inputs E1_Q_48

when  E1_Write_Enable  is "0"  outputs E1_Q_16
when  E1_Write_Enable  is "0"  outputs E1_Q_32
when  E1_Write_Enable  is "0"  outputs E1_Q_48

when  E2_Write_Enable  is "1"  inputs E2_Q_16
when  E2_Write_Enable  is "1"  inputs E2_Q_32
when  E2_Write_Enable  is "1"  inputs E2_Q_48

when  E2_Write_Enable  is "0"  outputs E2_Q_16
when  E2_Write_Enable  is "0"  outputs E2_Q_32
when  E2_Write_Enable  is "0"  outputs E2_Q_48

trace  E1_Q_16 to E1_Clock, E1_Data, E1_Write_Enable
trace  E1_Q_32 to E1_Clock, E1_Data, E1_Write_Enable
trace  E1_Q_32 to E1_Q_16
trace  E1_Q_48 to E1_Clock, E1_Data, E1_Write_Enable
trace  E1_Q_48 to E1_Q_16,E1_Q_32
trace  E1_Q_64 to E1_Clock, E1_Data, E1_Write_Enable
trace  E1_Q_64 to E1_Q_16,E1_Q_32,E1_Q_48

trace  E2_Q_16 to E2_Clock, E2_Data, E2_Write_Enable
trace  E2_Q_32 to E2_Clock, E2_Data, E2_Write_Enable
trace  E2_Q_32 to E2_Q_16
trace  E2_Q_48 to E2_Clock, E2_Data, E2_Write_Enable
trace  E2_Q_48 to E2_Q_16,E2_Q_32
trace  E2_Q_64 to E2_Clock, E2_Data, E2_Write_Enable
trace  E2_Q_64 to E2_Q_16,E2_Q_32,E2_Q_48

!**********************************************************************
!**********************************************************************

vector E1_Clock_Low
     set E1_Clock    to "0"
     set E1_Data     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_High
     set E1_Clock    to "1"
     set E1_Data     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_Low_Q_16
     drive E1_Q_16
     set E1_Clock    to "0"
     set E1_Q_16     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_High_Q_16
     drive E1_Q_16
     set E1_Clock    to "1"
     set E1_Q_16     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_Low_Q_32
     drive E1_Q_32
     set E1_Clock    to "0"
     set E1_Q_32     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_High_Q_32
     drive E1_Q_32
     set E1_Clock    to "1"
     set E1_Q_32     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_Low_Q_48
     drive E1_Q_48
     set E1_Clock    to "0"
     set E1_Q_48     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Clock_High_Q_48
     drive E1_Q_48
     set E1_Clock    to "1"
     set E1_Q_48     to "K"
     set E1_Write_Enable  to "K"
end vector

vector E1_Write_Enable_Low
     set E1_Clock    to "0"
     set E1_Write_Enable  to  "0"
end vector

vector E1_Write_Enable_High
     set E1_Clock    to "0"
     set E1_Write_Enable  to "1"
end vector

vector E1_Data_Low
     set E1_Clock    to "0"
     set E1_Data     to "0"
     set E1_Write_Enable  to "K"
end vector

vector E1_Data_High
     set E1_Clock    to "0"
     set E1_Data     to "1"
     set E1_Write_Enable  to "K"
end vector

vector E1_Toggle_Data
     set E1_Clock    to "0"
     set E1_Write_Enable  to "K"
     set E1_Data     to "T"
end vector

vector E1_Q_16_Drive_Low
     drive E1_Q_16
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_16     to "0"
end vector

vector E1_Q_16_Receive_Low
     receive E1_Q_16
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_16     to "0"
end vector

vector E1_Q_32_Drive_Low
     drive E1_Q_32
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_32     to "0"
end vector

vector E1_Q_32_Receive_Low
     receive E1_Q_32
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_32     to "0"
end vector

vector E1_Q_48_Drive_Low
     drive E1_Q_48
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_48     to "0"
end vector

vector E1_Q_48_Receive_Low
     receive E1_Q_48
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_48     to "0"
end vector

vector E1_Q_64_Receive_Low
     receive E1_Q_64
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_64     to "0"
end vector

vector E1_Q_16_Drive_High
     drive E1_Q_16
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_16     to "1"
end vector

vector E1_Q_16_Receive_High
     receive E1_Q_16
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_16     to "1"
end vector

vector E1_Q_32_Drive_High
     drive E1_Q_32
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_32     to "1"
end vector

vector E1_Q_32_Receive_High
     receive E1_Q_32
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_32     to "1"
end vector

vector E1_Q_48_Drive_High
     drive E1_Q_48
     set E1_Write_Enable  to "1"
     set E1_Clock    to "0"
     set E1_Q_48     to "1"
end vector

vector E1_Q_48_Receive_High
     receive E1_Q_48
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_48     to "1"
end vector

vector E1_Q_64_Receive_High
     receive E1_Q_64
     set E1_Write_Enable  to "0"
     set E1_Clock    to "0"
     set E1_Q_64     to "1"
end vector

vector E1_Q_16_Drive_Toggle
     drive E1_Q_16
     set E1_Write_Enable to "1"
     set E1_Clock    to "1"
     set E1_Q_16     to "T"
end vector

vector E1_Q_32_Drive_Toggle
     drive E1_Q_32
     set E1_Write_Enable to "1"
     set E1_Clock    to "1"
     set E1_Q_32     to "T"
end vector

vector E1_Q_48_Drive_Toggle
     drive E1_Q_48
     set E1_Write_Enable to "1"
     set E1_Clock    to "1"
     set E1_Q_48     to "T"
end vector


!*****************************************************************


vector E2_Clock_Low
     set E2_Clock    to "0"
     set E2_Data     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_High
     set E2_Clock    to "1"
     set E2_Data     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_Low_Q_16
     drive E2_Q_16
     set E2_Clock    to "0"
     set E2_Q_16     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_High_Q_16
     drive E2_Q_16
     set E2_Clock    to "1"
     set E2_Q_16     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_Low_Q_32
     drive E2_Q_32
     set E2_Clock    to "0"
     set E2_Q_32     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_High_Q_32
     drive E2_Q_32
     set E2_Clock    to "1"
     set E2_Q_32     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_Low_Q_48
     drive E2_Q_48
     set E2_Clock    to "0"
     set E2_Q_48     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Clock_High_Q_48
     drive E2_Q_48
     set E2_Clock    to "1"
     set E2_Q_48     to "K"
     set E2_Write_Enable  to "K"
end vector

vector E2_Write_Enable_Low
     set E2_Clock    to "0"
     set E2_Write_Enable  to  "0"
end vector

vector E2_Write_Enable_High
     set E2_Clock    to "0"
     set E2_Write_Enable  to "1"
end vector

vector E2_Data_Low
     set E2_Clock    to "0"
     set E2_Data     to "0"
     set E2_Write_Enable  to "K"
end vector

vector E2_Data_High
     set E2_Clock    to "0"
     set E2_Data     to "1"
     set E2_Write_Enable  to "K"
end vector

vector E2_Toggle_Data
     set E2_Clock    to "0"
     set E2_Write_Enable  to "K"
     set E2_Data     to "T"
end vector

vector E2_Q_16_Drive_Low
     drive E2_Q_16
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_16     to "0"
end vector

vector E2_Q_16_Receive_Low
     receive E2_Q_16
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_16     to "0"
end vector

vector E2_Q_32_Drive_Low
     drive E2_Q_32
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_32     to "0"
end vector

vector E2_Q_32_Receive_Low
     receive E2_Q_32
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_32     to "0"
end vector

vector E2_Q_48_Drive_Low
     drive E2_Q_48
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_48     to "0"
end vector

vector E2_Q_48_Receive_Low
     receive E2_Q_48
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_48     to "0"
end vector

vector E2_Q_64_Receive_Low
     receive E2_Q_64
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_64     to "0"
end vector

vector E2_Q_16_Drive_High
     drive E2_Q_16
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_16     to "1"
end vector

vector E2_Q_16_Receive_High
     receive E2_Q_16
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_16     to "1"
end vector

vector E2_Q_32_Drive_High
     drive E2_Q_32
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_32     to "1"
end vector

vector E2_Q_32_Receive_High
     receive E2_Q_32
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_32     to "1"
end vector

vector E2_Q_48_Drive_High
     drive E2_Q_48
     set E2_Write_Enable  to "1"
     set E2_Clock    to "0"
     set E2_Q_48     to "1"
end vector

vector E2_Q_48_Receive_High
     receive E2_Q_48
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_48     to "1"
end vector

vector E2_Q_64_Receive_High
     receive E2_Q_64
     set E2_Write_Enable  to "0"
     set E2_Clock    to "0"
     set E2_Q_64     to "1"
end vector

vector E2_Q_16_Drive_Toggle
     drive E2_Q_16
     set E2_Write_Enable to "1"
     set E2_Clock    to "1"
     set E2_Q_16     to "T"
end vector

vector E2_Q_32_Drive_Toggle
     drive E2_Q_32
     set E2_Write_Enable to "1"
     set E2_Clock    to "1"
     set E2_Q_32     to "T"
end vector

vector E2_Q_48_Drive_Toggle
     drive E2_Q_48
     set E2_Write_Enable to "1"
     set E2_Clock    to "1"
     set E2_Q_48     to "T"
end vector




!**********************************************************************
!**********************************************************************

!    Tested as two separate elements, E1 and E2

!    Each element has separate test units for each output.
!    WE_Low is assummed for each unit.
!    WE_High is tested as a seperate unit.


!    Test element E1

   unit   "E1 Test 16_bit output only"
     execute    E1_Write_Enable_Low
     execute    E1_Data_Low
       repeat 16 times
          execute    E1_Clock_High
          execute    E1_Clock_Low
          execute    E1_Toggle_Data
       end repeat
     execute     E1_Q_16_Receive_Low
     execute     E1_Clock_High
     execute     E1_Clock_Low
     execute     E1_Q_16_Receive_High
   end unit



   unit   "E1 Test 32_bit output only"
     execute    E1_Write_Enable_Low
     execute    E1_Data_Low
       repeat 32 times
          execute    E1_Clock_High
          execute    E1_Clock_Low
          execute    E1_Toggle_Data
       end repeat
     execute     E1_Q_32_Receive_Low
     execute     E1_Clock_High
     execute     E1_Clock_Low
     execute     E1_Q_32_Receive_High
   end unit



   unit   "E1 Test 48_bit output only"
     execute    E1_Write_Enable_Low
     execute    E1_Data_Low
       repeat 48 times
          execute    E1_Clock_High
          execute    E1_Clock_Low
          execute    E1_Toggle_Data
       end repeat
     execute     E1_Q_48_Receive_Low
     execute     E1_Clock_High
     execute     E1_Clock_Low
     execute     E1_Q_48_Receive_High
   end unit



   unit   "E1 Test 64_bit output only"
     execute    E1_Write_Enable_Low
     execute    E1_Data_Low
       repeat 64 times
          execute    E1_Clock_High
          execute    E1_Clock_Low
          execute    E1_Toggle_Data
       end repeat
     execute     E1_Q_64_Receive_Low
     execute     E1_Clock_High
     execute     E1_Clock_Low
     execute     E1_Q_64_Receive_High
   end unit


   unit  "E1 Test Write_Enable"
     execute    E1_Q_16_Drive_Low  !* see below
      repeat 16 times
       execute    E1_Clock_High_Q_16
       execute    E1_Clock_Low_Q_16
       execute    E1_Q_16_Drive_toggle  !*if Q_16 is not available, change
                                         ! Q_16 to Q_32 or Q_48
      end repeat
     execute      E1_Q_32_Receive_High  !**and change Q_32 to Q_48 or Q_64
     execute      E1_Clock_High_Q_16  !*see above
     execute      E1_Clock_Low_Q_16  !*see above
     execute      E1_Q_32_Receive_Low  !**see above
   end unit




!    Test element E2

   unit   "E2 Test 16_bit output only"
     execute    E2_Write_Enable_Low
     execute    E2_Data_Low
       repeat 16 times
          execute    E2_Clock_High
          execute    E2_Clock_Low
          execute    E2_Toggle_Data
       end repeat
     execute     E2_Q_16_Receive_Low
     execute     E2_Clock_High
     execute     E2_Clock_Low
     execute     E2_Q_16_Receive_High
   end unit



   unit   "E2 Test 32_bit output only"
     execute    E2_Write_Enable_Low
     execute    E2_Data_Low
       repeat 32 times
          execute    E2_Clock_High
          execute    E2_Clock_Low
          execute    E2_Toggle_Data
       end repeat
     execute     E2_Q_32_Receive_Low
     execute     E2_Clock_High
     execute     E2_Clock_Low
     execute     E2_Q_32_Receive_High
   end unit



   unit   "E2 Test 48_bit output only"
     execute    E2_Write_Enable_Low
     execute    E2_Data_Low
       repeat 48 times
          execute    E2_Clock_High
          execute    E2_Clock_Low
          execute    E2_Toggle_Data
       end repeat
     execute     E2_Q_48_Receive_Low
     execute     E2_Clock_High
     execute     E2_Clock_Low
     execute     E2_Q_48_Receive_High
   end unit



   unit   "E2 Test 64_bit output only"
     execute    E2_Write_Enable_Low
     execute    E2_Data_Low
       repeat 64 times
          execute    E2_Clock_High
          execute    E2_Clock_Low
          execute    E2_Toggle_Data
       end repeat
     execute     E2_Q_64_Receive_Low
     execute     E2_Clock_High
     execute     E2_Clock_Low
     execute     E2_Q_64_Receive_High
   end unit



   unit  "E2 Test Write_Enable"
     execute    E2_Q_16_Drive_Low  !* see below
      repeat 16 times
       execute    E2_Clock_High_Q_16
       execute    E2_Clock_Low_Q_16
       execute    E2_Q_16_Drive_toggle  !*if Q_16 is not available, change
                                         ! Q_16 to Q_32 or Q_48
      end repeat
     execute      E2_Q_32_Receive_High  !**and change Q_32 to Q_48 or Q_64
     execute      E2_Clock_High_Q_16  !*see above
     execute      E2_Clock_Low_Q_16  !*see above
     execute      E2_Q_32_Receive_Low  !**see above
   end unit









!    End of Test