!!!!    6    0    1  991661962  V601d                                         

!  $Log: <@(#) A.10.00  New library.> $

!-----------------------------------------------------------------------
!  Copyright (c) Hewlett-Packard Co. 1996
!
!  All Rights Reserved.  Reproduction, adaptation, or translation
!  without prior written permission is prohibited, except as allowed
!  under the copyright laws.
!
!-----------------------------------------------------------------------
!
! Device           : 74f655
! Function         : Octal Buffer Driver with Parity, Inverting (3-state)
! revision         : B.01.00
! safeguard        : high_out_fttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

! Manufacturer  : Philips
! Package       : 24-Pin DIP
! Test Platform : HP3070
!
!-----------------------------------------------------------------------
!
! Additional Information.
!
!       1.      Chip Marking: 74F655AN
!                             KQX0136
!                             9522hF
!
!       2.      Ordering Information:
!                       Part Number             Package
!
!                       N74F655AN               24-Pin Plastic Slim DIP
!                       N74F655AD               24-Pin Plastic SOL
!------------------------------------------------------------------------------

combinatorial

vector cycle 500n
receive delay 400n

assign   VCC         to pins  24
assign   GND         to pins  12

assign   Inputs      to pins  11, 10,  9,  8,  7,  6,  5,  4,  3
assign   D0_I        to pins   4            !AT Added for minimum pin test.
assign   D1_I        to pins   5            !AT Added for minimum pin test.
assign   D2_I        to pins   6            !AT Added for minimum pin test.
assign   D3_I        to pins   7            !AT Added for minimum pin test.
assign   D4_I        to pins   8            !AT Added for minimum pin test.
assign   D5_I        to pins   9            !AT Added for minimum pin test.
assign   D6_I        to pins  10            !AT Added for minimum pin test.
assign   D7_I        to pins  11            !AT Added for minimum pin test.

assign   Outputs     to pins  13, 14, 15, 16, 17, 18, 19, 20, 21, 22
assign   D0b_O       to pins  20            !AT Added for minimum pin test.
assign   D1b_O       to pins  19            !AT Added for minimum pin test.
assign   D2b_O       to pins  18            !AT Added for minimum pin test.
assign   D3b_O       to pins  17            !AT Added for minimum pin test.
assign   D4b_O       to pins  16            !AT Added for minimum pin test.
assign   D5b_O       to pins  15            !AT Added for minimum pin test.
assign   D6b_O       to pins  14            !AT Added for minimum pin test.
assign   D7b_O       to pins  13            !AT Added for minimum pin test.

assign   OE_BAR_0    to pins   1
assign   OE_BAR_1    to pins   2
assign   OE_BAR_2    to pins  23
assign   OE_BAR_ALL  to pins   1,  2, 23

family   TTL

power    VCC, GND

inputs   Inputs, OE_BAR_0, OE_BAR_1, OE_BAR_2, OE_BAR_ALL
inputs   D0_I, D1_I, D2_I, D3_I       !AT Added for minimum pin test.
inputs   D4_I, D5_I, D6_I, D7_I       !AT Added for minimum pin test.

outputs  Outputs
outputs  D0b_O, D1b_O, D2b_O, D3b_O   !AT Added for minimum pin test.
outputs  D4b_O, D5b_O, D6b_O, D7b_O   !AT Added for minimum pin test.

disable  Outputs             with OE_BAR_0 to "1"
disable  Outputs             with OE_BAR_1 to "1"
disable  Outputs             with OE_BAR_2 to "1"

outputs  limited  to  1  at  "0", 1  at  "1"

trace Outputs  to Inputs

when    OE_BAR_0 is "1"  inactive Outputs
when    OE_BAR_1 is "1"  inactive Outputs
when    OE_BAR_2 is "1"  inactive Outputs

!
!-----------------------------------------------------------------------
!

vector  Inputs_000000000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000000000"
   set   Outputs     to "1111111110"
end vector

vector  Inputs_000000001
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000000001"
   set   Outputs     to "1111111101"
end vector

vector  Inputs_000000011
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000000011"
   set   Outputs     to "1111111010"
end vector

vector  Inputs_000000111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000000111"
   set   Outputs     to "1111110001"
end vector

vector  Inputs_000001111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000001111"
   set   Outputs     to "1111100010"
end vector

vector  Inputs_000011111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000011111"
   set   Outputs     to "1111000001"
end vector

vector  Inputs_000111111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "000111111"
   set   Outputs     to "1110000010"
end vector

vector  Inputs_001111111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "001111111"
   set   Outputs     to "1100000001"
end vector

vector  Inputs_011111111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "011111111"
   set   Outputs     to "1000000010"
end vector

vector  Inputs_111111111
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111111111"
   set   Outputs     to "0000000001"
end vector

vector  Inputs_111111110
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111111110"
   set   Outputs     to "0000000010"
end vector

vector  Inputs_111111100
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111111100"
   set   Outputs     to "0000000101"
end vector

vector  Inputs_111111000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111111000"
   set   Outputs     to "0000001110"
end vector

vector  Inputs_111110000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111110000"
   set   Outputs     to "0000011101"
end vector

vector  Inputs_111100000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111100000"
   set   Outputs     to "0000111110"
end vector

vector  Inputs_111000000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "111000000"
   set   Outputs     to "0001111101"
end vector

vector  Inputs_110000000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "110000000"
   set   Outputs     to "0011111110"
end vector

vector  Inputs_100000000
   set   OE_BAR_ALL  to "000"
   set   Inputs      to "100000000"
   set   Outputs     to "0111111101"
end vector

!------------------------------------------------------------------
!   Vectors for checking Enable pins
!------------------------------------------------------------------

vector  Enable_001
   set   OE_BAR_ALL  to "001"
   set   Inputs      to "101010101"
   set   Outputs     to "1111111111"
end vector

vector  Enable_010
   set   OE_BAR_ALL  to "010"
   set   Inputs      to "101010101"
   set   Outputs     to "1111111111"
end vector

vector  Enable_100
   set   OE_BAR_ALL  to "100"
   set   Inputs      to "101010101"
   set   Outputs     to "1111111111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  D0_I_0
   set   OE_BAR_ALL  to "000"
   set   D0_I        to "0"
   set   D0b_O       to "1"
end vector

vector  D0_I_1
   set   OE_BAR_ALL  to "000"
   set   D0_I        to "1"
   set   D0b_O       to "0"
end vector

vector  D1_I_0
   set   OE_BAR_ALL  to "000"
   set   D1_I        to "0"
   set   D1b_O       to "1"
end vector

vector  D1_I_1
   set   OE_BAR_ALL  to "000"
   set   D1_I        to "1"
   set   D1b_O       to "0"
end vector

vector  D2_I_0
   set   OE_BAR_ALL  to "000"
   set   D2_I        to "0"
   set   D2b_O       to "1"
end vector

vector  D2_I_1
   set   OE_BAR_ALL  to "000"
   set   D2_I        to "1"
   set   D2b_O       to "0"
end vector

vector  D3_I_0
   set   OE_BAR_ALL  to "000"
   set   D3_I        to "0"
   set   D3b_O       to "1"
end vector

vector  D3_I_1
   set   OE_BAR_ALL  to "000"
   set   D3_I        to "1"
   set   D3b_O       to "0"
end vector

vector  D4_I_0
   set   OE_BAR_ALL  to "000"
   set   D4_I        to "0"
   set   D4b_O       to "1"
end vector

vector  D4_I_1
   set   OE_BAR_ALL  to "000"
   set   D4_I        to "1"
   set   D4b_O       to "0"
end vector

vector  D5_I_0
   set   OE_BAR_ALL  to "000"
   set   D5_I        to "0"
   set   D5b_O       to "1"
end vector

vector  D5_I_1
   set   OE_BAR_ALL  to "000"
   set   D5_I        to "1"
   set   D5b_O       to "0"
end vector

vector  D6_I_0
   set   OE_BAR_ALL  to "000"
   set   D6_I        to "0"
   set   D6b_O       to "1"
end vector

vector  D6_I_1
   set   OE_BAR_ALL  to "000"
   set   D6_I        to "1"
   set   D6b_O       to "0"
end vector

vector  D7_I_0
   set   OE_BAR_ALL  to "000"
   set   D7_I        to "0"
   set   D7b_O       to "1"
end vector

vector  D7_I_1
   set   OE_BAR_ALL  to "000"
   set   D7_I        to "1"
   set   D7b_O       to "0"
end vector

!
!-----------------------------------------------------------------------
!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 Test"
   execute  D0_I_0
   execute  D0_I_1
end unit

unit "awaretest D1 Test"
   execute  D1_I_0
   execute  D1_I_1
end unit

unit "awaretest D2 Test"
   execute  D2_I_0
   execute  D2_I_1
end unit

unit "awaretest D3 Test"
   execute  D3_I_0
   execute  D3_I_1
end unit

unit "awaretest D4 Test"
   execute  D4_I_0
   execute  D4_I_1
end unit

unit "awaretest D5 Test"
   execute  D5_I_0
   execute  D5_I_1
end unit

unit "awaretest D6 Test"
   execute  D6_I_0
   execute  D6_I_1
end unit

unit "awaretest D7 Test"
   execute  D7_I_0
   execute  D7_I_1
end unit

! Inputs applied in Gray Code format to reduce transients

unit  "Parity_Bus_Driver_000"
   execute  Inputs_000000000
   execute  Inputs_000000001
   execute  Inputs_000000011
   execute  Inputs_000000111
   execute  Inputs_000001111
   execute  Inputs_000011111
   execute  Inputs_000111111
   execute  Inputs_001111111
   execute  Inputs_011111111
   execute  Inputs_111111111
   execute  Inputs_111111110
   execute  Inputs_111111100
   execute  Inputs_111111000
   execute  Inputs_111110000
   execute  Inputs_111100000
   execute  Inputs_111000000
   execute  Inputs_110000000
   execute  Inputs_100000000
end unit

! The Enable pins are verified in the following unit

unit  disable test "Parity_Bus_Driver_001_010_100"
   execute  Enable_001
   execute  Enable_010
   execute  Enable_100
end unit

!
!  End of test
!