!!!! 6 0 1 990111849 V0b21 ! Device : 2732 ! Function : uv_prom 3-state 4k x 8 ! revision : B.01.00 ! safeguard : med_out_mos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential warning "Pull-ups are required to test high-impedance outputs." vector cycle 600n receive delay 500n assign VCC to pins 24 assign GND to pins 12 assign Address_bus to pins 21,19,22,23,1,2,3,4,5,6,7,8 assign Data_bus to pins 17,16,15,14,13,11,10,9 assign Data_D0 to pins 9 !AT Added for minimum pin test. assign Data_D1 to pins 10 !AT Added for minimum pin test. assign Data_D2 to pins 11 !AT Added for minimum pin test. assign Data_D3 to pins 13 !AT Added for minimum pin test. assign Data_D4 to pins 14 !AT Added for minimum pin test. assign Data_D5 to pins 15 !AT Added for minimum pin test. assign Data_D6 to pins 16 !AT Added for minimum pin test. assign Data_D7 to pins 17 !AT Added for minimum pin test. assign Output_Enable to pins 20 assign Chip_Enable to pins 18 family TTL power VCC, GND inputs Address_bus, Output_Enable, Chip_Enable outputs Data_bus outputs Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test. outputs Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test. when Chip_Enable is "1" inactive Data_bus when Output_enable is "1" inactive Data_bus trace Data_bus to Address_bus,Output_Enable,Chip_Enable disable Data_bus with Chip_Enable to "1" disable Data_bus with Output_Enable to "1" set load on groups Data_bus to pull up !**************************************************************************** !**************************************************************************** vector Address_Counter set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_bus to "00000000" upcounter Address_bus end vector vector Address_Counter_2 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "111100000000" set Data_bus to "00000000" upcounter Address_bus end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Address_Counter_D0 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D0 to "0" upcounter Address_bus end vector vector Address_Counter_D1 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D1 to "0" upcounter Address_bus end vector vector Address_Counter_D2 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D2 to "0" upcounter Address_bus end vector vector Address_Counter_D3 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D3 to "0" upcounter Address_bus end vector vector Address_Counter_D4 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D4 to "0" upcounter Address_bus end vector vector Address_Counter_D5 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D5 to "0" upcounter Address_bus end vector vector Address_Counter_D6 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D6 to "0" upcounter Address_bus end vector vector Address_Counter_D7 set Chip_Enable to "0" set Output_Enable to "0" set Address_bus to "000000000000" set Data_D7 to "0" upcounter Address_bus end vector !**************************************************************************** !**************************************************************************** !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" preset counter Address_Counter_D0 compress repeat 255 times count Address_Counter_D0 compress end repeat end unit unit "awaretest D1 Test" preset counter Address_Counter_D1 compress repeat 255 times count Address_Counter_D1 compress end repeat end unit unit "awaretest D2 Test" preset counter Address_Counter_D2 compress repeat 255 times count Address_Counter_D2 compress end repeat end unit unit "awaretest D3 Test" preset counter Address_Counter_D3 compress repeat 255 times count Address_Counter_D3 compress end repeat end unit unit "awaretest D4 Test" preset counter Address_Counter_D4 compress repeat 255 times count Address_Counter_D4 compress end repeat end unit unit "awaretest D5 Test" preset counter Address_Counter_D5 compress repeat 255 times count Address_Counter_D5 compress end repeat end unit unit "awaretest D6 Test" preset counter Address_Counter_D6 compress repeat 255 times count Address_Counter_D6 compress end repeat end unit unit "awaretest D7 Test" preset counter Address_Counter_D7 compress repeat 255 times count Address_Counter_D7 compress end repeat end unit ! ROM contents are partially verified by performing CRC check of the ! outputs while a counter cycles through the upper and lower 500 address ! locations. Results are compared against those of a known good board. unit "ROM Test lower" preset counter Address_Counter compress repeat 512 times count Address_Counter compress end repeat end unit unit "ROM Test upper" preset counter Address_Counter_2 compress repeat 512 times count Address_Counter_2 compress end repeat end unit ! End of Test