!!!!    6    0    1  991772599  Veed1                                         

! Device           : 74ls395
! Function         : shift_register 3-state 4-bit_universal
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign  VCC         to pins 16
assign  GND         to pins 8

assign  Parallel_inputs to pins 3,4,5,6
assign  Serial_input    to pins 2

assign  Outputs     to pins 15,14,13,12
assign  D0          to pins 12          !AT Added for minimum pin test.
assign  D1          to pins 13          !AT Added for minimum pin test.
assign  D2          to pins 14          !AT Added for minimum pin test.
assign  D3          to pins 15          !AT Added for minimum pin test.

assign  D_prime_out to pins 11

assign  Clock       to pins 10
assign  Clear_bar   to pins 1
assign  Shift_load  to pins 7
assign  Output_enable_bar to pins 9

family  TTL

power   VCC, GND

inputs  Parallel_inputs, Serial_input, Clock, Clear_bar
inputs  Shift_load, Output_enable_bar

outputs Outputs, D_prime_out
outputs D0, D1, D2, D3          !AT Added for minimum pin test.


disable Outputs     with Output_enable_bar  to "1"

when Output_enable_bar is "1" inactive Outputs

trace Outputs to Parallel_inputs, Serial_input, Clock, Clear_bar
trace Outputs to Shift_load, Output_enable_bar
trace D_prime_out to Parallel_inputs, Serial_input, Clock, Clear_bar
trace D_prime_out to Shift_load, Output_enable_bar

!*********************************************************************
!*********************************************************************

vector    Clear_low
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Clear_bar           to "0"
     set  Outputs             to "0000"
     set  D_prime_out         to "0"
end vector

vector    Clear_low_ksd
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Clear_bar           to "0"
     set  Serial_input        to "k"
     set  Outputs             to "0000"
     set  D_prime_out         to "0"
end vector

vector    Clock_low
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "0"
end vector

vector    Clock_high__load
     set  Clear_bar           to "1"
     set  Shift_load          to "1"
     set  Parallel_inputs     to "kkkk"
     set  Clock               to "1"
end vector

vector    Clock_high__serial
     set  Clear_bar           to "1"
     set  Shift_load          to "0"
     set  Serial_input         to "k"
     set  Clock               to "1"
end vector

vector    Clock_high__shift
     set  Clear_bar           to "1"
     set  Shift_load          to "0"
     set  Clock               to "1"
end vector

vector    Outputs_0101_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Outputs             to "0101"
     set  D_prime_out         to "1"
end vector

vector    Outputs_0101_1_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  Outputs             to "0101"
     set  D_prime_out         to "1"
end vector

vector    Outputs_1010_0
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Outputs             to "1010"
     set  D_prime_out         to "0"
end vector

vector    Outputs_1010_0_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  Outputs             to "1010"
     set  D_prime_out         to "0"
end vector

vector    Outputs_1111_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Outputs             to "1111"
     set  D_prime_out         to "1"
end vector

vector    Outputs_X101_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Outputs             to "X101"
     set  D_prime_out         to "1"
end vector

vector    Parallel_inputs_0101
     set  Clear_bar           to "1"
     set  Shift_load          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "0101"
end vector

vector    Parallel_inputs_1010
     set  Clear_bar           to "1"
     set  Shift_load          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "1010"
end vector

vector    Parallel_inputs_1111
     set  Clear_bar           to "1"
     set  Shift_load          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "1111"
end vector

vector    Parallel_inputs_0000
     set  Clear_bar           to "1"
     set  Shift_load          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "0000"
end vector

vector    Serial_input_high
     set  Clear_bar           to "1"
     set  Shift_load          to "0"
     set  Clock               to "1"
     set  Serial_input        to "1"
end vector

vector    Serial_input_low
     set  Clear_bar           to "1"
     set  Shift_load          to "0"
     set  Clock               to "1"
     set  Serial_input        to "0"
end vector

vector    Shift_load_low
     set  Clear_bar           to "1"
     set  Clock               to "1"
     set  Shift_load          to "0"
end vector



!*****VECTORS FOR DISABLE TESTS*****



vector    Outputs_1010_0_ksd_Disabled
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "1"
     set  Serial_input        to "k"
     set  Outputs             to "1010"
     set  D_prime_out         to "0"
end vector

vector    Outputs_0101_1_ksd_Disabled
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "1"
     set  Serial_input        to "k"
     set  Outputs             to "0101"
     set  D_prime_out         to "1"
end vector

vector    Output_enable_bar_low
     set  Output_enable_bar   to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    D0_0
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D0                  to "0"
end vector

vector    D0_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D0                  to "1"
end vector

vector    D1_0
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D1                  to "0"
end vector

vector    D1_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D1                  to "1"
end vector

vector    D2_0
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D2                  to "0"
end vector

vector    D2_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D2                  to "1"
end vector

vector    D3_0
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D3                  to "0"
end vector

vector    D3_1
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  D3                  to "1"
end vector

vector    D0_0_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D0                  to "0"
end vector

vector    D0_1_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D0                  to "1"
end vector

vector    D1_0_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D1                  to "0"
end vector

vector    D1_1_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D1                  to "1"
end vector

vector    D2_0_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D2                  to "0"
end vector

vector    D2_1_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D2                  to "1"
end vector

vector    D3_0_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D3                  to "0"
end vector

vector    D3_1_ksd
     set  Clear_bar           to "1"
     set  Shift_load          to "k"
     set  Clock               to "1"
     set  Output_enable_bar   to "0"
     set  Serial_input        to "k"
     set  D3                  to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_high)
     execute   Clock_high
     execute   Clock_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D0_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D0_1_ksd
end unit

unit "awaretest D1 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D1_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D1_1_ksd
end unit

unit "awaretest D2 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D2_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D2_1_ksd
end unit

unit "awaretest D3 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D3_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   D3_1_ksd
end unit

unit "awaretest D0 parallel inputs Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D0_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D0_1
end unit

unit "awaretest D1 parallel inputs Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D1_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D1_1
end unit

unit "awaretest D2 parallel inputs Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D2_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D2_1
end unit

unit "awaretest D3 parallel inputs Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D3_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D3_1
end unit

!****************************************************************

unit "test serial input"
     repeat    2 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Outputs_1010_0_ksd
     execute   Serial_input_low
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_0101_1_ksd
     execute   Serial_input_high
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_1010_0_ksd
end unit

unit "test parallel inputs"
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101_1
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010_0
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101_1
end unit

unit "test parallel inputs, shift right"
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101_1
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010_0
     execute   Shift_load_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X101_1
end unit

unit "test clear, serial input"
     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Clear_low_ksd
end unit

unit "test clear, parallel input"
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1111_1
     execute   Clear_low
end unit

unit "circular shift, D_prime_out tied to Serial input"
     tied      Serial_input, D_prime_out
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101_1
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010_0
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101_1
     execute   Shift_load_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_1010_0
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_0101_1
end unit



!*****TESTS FOR DISABLE **************************



unit disable test "Disable Test for serial input"
     repeat    2 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_high__serial)
          execute   Serial_input_high
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Outputs_1010_0_ksd_Disabled
     execute   Output_enable_bar_low
     execute   Serial_input_low
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_0101_1_ksd_Disabled
     execute   Output_enable_bar_low
     execute   Serial_input_high
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_1010_0_ksd_Disabled
end unit


!    End of test