!!!!    6    0    1  991764167  Vd53a                                         

! Device           : 74hc256
! Function         : dual 4 bit addressable latch
! revision         : B.01.00
! safeguard        : high_out_hcmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle         500n
receive delay        400n

assign   VCC         to pins  16
assign   GND         to pins  8

assign   Address     to pins  2,1
assign   Data_A      to pins  3
assign   Data_B      to pins  13
assign   Clear_bar   to pins  15
assign   Enable_bar  to pins  14

assign   Outputs_A   to pins  7,6,5,4
assign   A_D0        to pins  4          !AT Added for minimum pin test.
assign   A_D1        to pins  5          !AT Added for minimum pin test.
assign   A_D2        to pins  6          !AT Added for minimum pin test.
assign   A_D3        to pins  7          !AT Added for minimum pin test.

assign   Outputs_B   to pins  12,11,10,9
assign   B_D0        to pins  9          !AT Added for minimum pin test.
assign   B_D1        to pins  10         !AT Added for minimum pin test.
assign   B_D2        to pins  11         !AT Added for minimum pin test.
assign   B_D3        to pins  12         !AT Added for minimum pin test.

family   CMOS

power    VCC,GND

inputs   Address,Data_A,Data_B,Clear_bar,Enable_bar

outputs  Outputs_A,Outputs_B
outputs  A_D0, A_D1, A_D2, A_D3          !AT Added for minimum pin test.
outputs  B_D0, B_D1, B_D2, B_D3          !AT Added for minimum pin test.

trace Outputs_A to Address,Data_A,Clear_bar,Enable_bar
trace Outputs_B to Address,Data_B,Clear_bar,Enable_bar
!*******************************************************************************
!*******************************************************************************

vector  Initialize_inputs
   set   Address     to "11"
   set   Clear_bar   to "1"
   set   Enable_bar  to "1"
   set   Data_A      to "1"
   set   Data_B      to "1"
end vector

vector  Keep_inputs
   set   Address     to "kk"
   set   Clear_bar   to "k"
   set   Enable_bar  to "k"
   set   Data_A      to "k"
   set   Data_B      to "k"
end vector

vector  Clear_true
   initialize        to Keep_inputs
   set   Clear_bar   to "0"
end vector

vector  Clear_false
   initialize        to Keep_inputs
   set   Clear_bar   to "1"
end vector

vector  Enable_true
   initialize        to Keep_inputs
   set   Enable_bar  to "0"
end vector

vector  Enable_false
   initialize        to Keep_inputs
   set   Enable_bar  to "1"
end vector

vector  Data_A_high
   initialize        to Keep_inputs
   set   Data_A      to "1"
end vector

vector  Data_A_low
   initialize        to Keep_inputs
   set   Data_A      to "0"
end vector

vector  Data_B_high
   initialize        to Keep_inputs
   set   Data_B      to "1"
end vector

vector  Data_B_low
   initialize        to Keep_inputs
   set   Data_B      to "0"
end vector

vector  Address_0
   initialize        to Keep_inputs
   set   Address     to "00"
end vector

vector  Address_1
   initialize        to Keep_inputs
   set   Address     to "01"
end vector

vector  Address_2
   initialize        to Keep_inputs
   set   Address     to "10"
end vector

vector  Address_3
   initialize        to Keep_inputs
   set   Address     to "11"
end vector

vector  Outputs_A_0000
   initialize        to Keep_inputs
   set   Outputs_A   to "0000"
end vector

vector  Outputs_A_0001
   initialize        to Keep_inputs
   set   Outputs_A   to "0001"
end vector

vector  Outputs_A_0010
   initialize        to Keep_inputs
   set   Outputs_A   to "0010"
end vector

vector  Outputs_A_0011
   initialize        to Keep_inputs
   set   Outputs_A   to "0011"
end vector

vector  Outputs_A_0100
   initialize        to Keep_inputs
   set   Outputs_A   to "0100"
end vector

vector  Outputs_A_0111
   initialize        to Keep_inputs
   set   Outputs_A   to "0111"
end vector

vector  Outputs_A_1000
   initialize        to Keep_inputs
   set   Outputs_A   to "1000"
end vector

vector  Outputs_A_1100
   initialize        to Keep_inputs
   set   Outputs_A   to "1100"
end vector

vector  Outputs_A_1110
   initialize        to Keep_inputs
   set   Outputs_A   to "1110"
end vector

vector  Outputs_A_1111
   initialize        to Keep_inputs
   set   Outputs_A   to "1111"
end vector
vector  Outputs_B_0000
   initialize        to Keep_inputs
   set   Outputs_B   to "0000"
end vector

vector  Outputs_B_0001
   initialize        to Keep_inputs
   set   Outputs_B   to "0001"
end vector

vector  Outputs_B_0010
   initialize        to Keep_inputs
   set   Outputs_B   to "0010"
end vector

vector  Outputs_B_0011
   initialize        to Keep_inputs
   set   Outputs_B   to "0011"
end vector

vector  Outputs_B_0100
   initialize        to Keep_inputs
   set   Outputs_B   to "0100"
end vector

vector  Outputs_B_0111
   initialize        to Keep_inputs
   set   Outputs_B   to "0111"
end vector

vector  Outputs_B_1000
   initialize        to Keep_inputs
   set   Outputs_B   to "1000"
end vector

vector  Outputs_B_1100
   initialize        to Keep_inputs
   set   Outputs_B   to "1100"
end vector

vector  Outputs_B_1110
   initialize        to Keep_inputs
   set   Outputs_B   to "1110"
end vector

vector  Outputs_B_1111
   initialize        to Keep_inputs
   set   Outputs_B   to "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  A_D0_0
   initialize        to Keep_inputs
   set   A_D0        to "0"
end vector

vector  A_D0_1
   initialize        to Keep_inputs
   set   A_D0        to "1"
end vector

vector  A_D1_0
   initialize        to Keep_inputs
   set   A_D1        to "0"
end vector

vector  A_D1_1
   initialize        to Keep_inputs
   set   A_D1        to "1"
end vector

vector  A_D2_0
   initialize        to Keep_inputs
   set   A_D2        to "0"
end vector

vector  A_D2_1
   initialize        to Keep_inputs
   set   A_D2        to "1"
end vector

vector  A_D3_0
   initialize        to Keep_inputs
   set   A_D3        to "0"
end vector

vector  A_D3_1
   initialize        to Keep_inputs
   set   A_D3        to "1"
end vector

vector  B_D0_0
   initialize        to Keep_inputs
   set   B_D0        to "0"
end vector

vector  B_D0_1
   initialize        to Keep_inputs
   set   B_D0        to "1"
end vector

vector  B_D1_0
   initialize        to Keep_inputs
   set   B_D1        to "0"
end vector

vector  B_D1_1
   initialize        to Keep_inputs
   set   B_D1        to "1"
end vector

vector  B_D2_0
   initialize        to Keep_inputs
   set   B_D2        to "0"
end vector

vector  B_D2_1
   initialize        to Keep_inputs
   set   B_D2        to "1"
end vector

vector  B_D3_0
   initialize        to Keep_inputs
   set   B_D3        to "0"
end vector

vector  B_D3_1
   initialize        to Keep_inputs
   set   B_D3        to "1"
end vector

!*******************************************************************************
!*******************************************************************************

sub  Clock
   execute  Enable_true
   execute  Enable_false
end sub

!*******************************************************************************
!*******************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with A D0.

unit "awaretest A_D0 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  A_D0_0
   execute  Enable_true
   execute  Address_0
   execute  A_D0_1
end unit

unit "awaretest A_D1 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  A_D1_0
   execute  Enable_true
   execute  Address_1
   execute  A_D1_1
end unit

unit "awaretest A_D2 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  A_D2_0
   execute  Enable_true
   execute  Address_2
   execute  A_D2_1
end unit

unit "awaretest A_D3 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  A_D3_0
   execute  Enable_true
   execute  Address_3
   execute  A_D3_1
end unit

unit "awaretest B_D0 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  B_D0_0
   execute  Enable_true
   execute  Address_0
   execute  B_D0_1
end unit

unit "awaretest B_D1 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  B_D1_0
   execute  Enable_true
   execute  Address_1
   execute  B_D1_1
end unit

unit "awaretest B_D2 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  B_D2_0
   execute  Enable_true
   execute  Address_2
   execute  B_D2_1
end unit

unit "awaretest B_D3 Test"
   execute  Initialize_inputs
   execute  Clear_true
   execute  B_D3_0
   execute  Enable_true
   execute  Address_3
   execute  B_D3_1
end unit

!****************************************************************

unit  "Test latch A clear"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Outputs_A_0000
end unit

unit  "Test latch A demultiplex"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Enable_true
   execute  Address_0
   execute  Outputs_A_0001
   execute  Address_1
   execute  Outputs_A_0010
   execute  Address_2
   execute  Outputs_A_0100
   execute  Address_3
   execute  Outputs_A_1000
end unit

unit  "Test latch A addressable"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Outputs_A_0000
   execute  Clear_false
   execute  Data_A_high
   execute  Address_0
   call  Clock
   execute  Outputs_A_0001
   execute  Address_1
   call  Clock
   execute  Outputs_A_0011
   execute  Address_2
   call  Clock
   execute  Outputs_A_0111
   execute  Address_3
   call  Clock
   execute  Outputs_A_1111
   execute  Data_A_low
   execute  Address_0
   call  Clock
   execute  Outputs_A_1110
   execute  Address_1
   call  Clock
   execute  Outputs_A_1100
   execute  Address_2
   call  Clock
   execute  Outputs_A_1000
   execute  Address_3
   call  Clock
   execute  Outputs_A_0000
end unit

unit  "Test latch B clear"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Outputs_B_0000
end unit

unit  "Test latch B demultiplex"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Enable_true
   execute  Address_0
   execute  Outputs_B_0001
   execute  Address_1
   execute  Outputs_B_0010
   execute  Address_2
   execute  Outputs_B_0100
   execute  Address_3
   execute  Outputs_B_1000
end unit

unit  "Test latch B addressable"
   execute  Initialize_inputs
   execute  Clear_true
   execute  Outputs_B_0000
   execute  Clear_false
   execute  Data_B_high
   execute  Address_0
   call  Clock
   execute  Outputs_B_0001
   execute  Address_1
   call  Clock
   execute  Outputs_B_0011
   execute  Address_2
   call  Clock
   execute  Outputs_B_0111
   execute  Address_3
   call  Clock
   execute  Outputs_B_1111
   execute  Data_B_low
   execute  Address_0
   call  Clock
   execute  Outputs_B_1110
   execute  Address_1
   call  Clock
   execute  Outputs_B_1100
   execute  Address_2
   call  Clock
   execute  Outputs_B_1000
   execute  Address_3
   call  Clock
   execute  Outputs_B_0000
end unit

! end of test