!!!!    6    0    1  991864857  V235e                                         

! Device           : 4562
! Function         : Shift_Register totem 128_Bit
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1.7u
receive delay 1.6u

assign VDD           to pins 14
assign VSS           to pins  7

assign Clock         to pins 5
assign Data          to pins 12
assign Outputs       to pins 3,6,2,8,1,9,13,10
assign D0            to pins 10         !AT Added for minimum pin test.
assign D1            to pins 13         !AT Added for minimum pin test.
assign D2            to pins  9         !AT Added for minimum pin test.
assign D3            to pins  1         !AT Added for minimum pin test.
assign D4            to pins  8         !AT Added for minimum pin test.
assign D5            to pins  2         !AT Added for minimum pin test.
assign D6            to pins  6         !AT Added for minimum pin test.
assign D7            to pins  3         !AT Added for minimum pin test.

assign NC            to pins 4,11

power VDD, VSS
family CMOS

inputs Clock, Data
outputs Outputs
outputs D0, D1, D2, D3          !AT Added for minimum pin test.
outputs D4, D5, D6, D7          !AT Added for minimum pin test.

nondigital  NC

trace  Outputs to  Clock, Data

!************************************************************************
!************************************************************************

vector Clock_High
     set Data        to "K"
     set Clock       to "1"
end vector

vector Clock_Low
     set Data        to "K"
     set Clock       to "0"
end vector

vector Data_Low
     set Clock       to "0"
     set Data        to "0"
end vector

vector Data_High
     set Clock       to "0"
     set Data        to "1"
end vector

vector Outputs_00000000
     set Data        to "K"
     set Clock       to "0"
     set Outputs     to "00000000"
end vector

vector Outputs_11111111
     set Data        to "K"
     set Clock       to "0"
     set Outputs     to "11111111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector D0_0
     set Data        to "K"
     set Clock       to "0"
     set D0          to "0"
end vector

vector D0_1
     set Data        to "K"
     set Clock       to "0"
     set D0          to "1"
end vector

vector D1_0
     set Data        to "K"
     set Clock       to "0"
     set D1          to "0"
end vector

vector D1_1
     set Data        to "K"
     set Clock       to "0"
     set D1          to "1"
end vector

vector D2_0
     set Data        to "K"
     set Clock       to "0"
     set D2          to "0"
end vector

vector D2_1
     set Data        to "K"
     set Clock       to "0"
     set D2          to "1"
end vector

vector D3_0
     set Data        to "K"
     set Clock       to "0"
     set D3          to "0"
end vector

vector D3_1
     set Data        to "K"
     set Clock       to "0"
     set D3          to "1"
end vector

vector D4_0
     set Data        to "K"
     set Clock       to "0"
     set D4          to "0"
end vector

vector D4_1
     set Data        to "K"
     set Clock       to "0"
     set D4          to "1"
end vector

vector D5_0
     set Data        to "K"
     set Clock       to "0"
     set D5          to "0"
end vector

vector D5_1
     set Data        to "K"
     set Clock       to "0"
     set D5          to "1"
end vector

vector D6_0
     set Data        to "K"
     set Clock       to "0"
     set D6          to "0"
end vector

vector D6_1
     set Data        to "K"
     set Clock       to "0"
     set D6          to "1"
end vector

vector D7_0
     set Data        to "K"
     set Clock       to "0"
     set D7          to "0"
end vector

vector D7_1
     set Data        to "K"
     set Clock       to "0"
     set D7          to "1"
end vector

!***********************************************************************
!***********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D0_0

     execute Clock_High
     execute Clock_Low
     execute D0_1
end unit

unit "awaretest D1 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D1_0

     execute Clock_High
     execute Clock_Low
     execute D1_1
end unit

unit "awaretest D2 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D2_0

     execute Clock_High
     execute Clock_Low
     execute D2_1
end unit

unit "awaretest D3 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D3_0

     execute Clock_High
     execute Clock_Low
     execute D3_1
end unit

unit "awaretest D4 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D4_0

     execute Clock_High
     execute Clock_Low
     execute D4_1
end unit

unit "awaretest D5 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D5_0

     execute Clock_High
     execute Clock_Low
     execute D5_1
end unit

unit "awaretest D6 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D6_0

     execute Clock_High
     execute Clock_Low
     execute D6_1
end unit

unit "awaretest D7 shift Test"
     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute D7_0

     execute Clock_High
     execute Clock_Low
     execute D7_1
end unit

!***********************************************************************

unit "Shift register test"

     repeat 64 times
          execute Data_Low
          execute Clock_High
          execute Clock_Low
          execute Data_High
          execute Clock_High
          execute Clock_Low
     end repeat
     execute Outputs_00000000

     execute Clock_High
     execute Clock_Low
     execute Outputs_11111111

end unit


!    End of Test