!!!!    6    0    1  991854587  V668f                                         

! Device           : 4580
! Function         : Register 3_State multiport_4_by_4
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

warning  " Pullups are required for Outputs in high impedance state."

sequential

vector cycle 5u
receive delay 4.9u

assign VDD           to pins 24
assign VSS           to pins 12

assign Clock         to pins 16
assign Write_Enable  to pins 15
assign Data_Input    to pins 17,18,19,20
assign D0            to pins 20         !AT Added for minimum pin test.
assign D1            to pins 19         !AT Added for minimum pin test.
assign D2            to pins 18         !AT Added for minimum pin test.
assign D3            to pins 17         !AT Added for minimum pin test.

assign Write_Address to pins 9,8
assign E1_Read_Address to pins 14,13
assign E2_Read_Address to pins 10,11
assign E1_Outputs    to pins 7,6,5,4
assign E1_D0         to pins 4          !AT Added for minimum pin test.
assign E1_D1         to pins 5          !AT Added for minimum pin test.
assign E1_D2         to pins 6          !AT Added for minimum pin test.
assign E1_D3         to pins 7          !AT Added for minimum pin test.

assign E2_Outputs    to pins 1,2,23,22
assign E2_D0         to pins 22         !AT Added for minimum pin test.
assign E2_D1         to pins 23         !AT Added for minimum pin test.
assign E2_D2         to pins 2          !AT Added for minimum pin test.
assign E2_D3         to pins 1          !AT Added for minimum pin test.

assign E1_Disable    to pins 3
assign E2_Disable    to pins 21

power  VDD, VSS
family  CMOS

inputs Clock, Write_Enable, Data_Input, Write_Address
inputs E1_Read_Address, E2_Read_Address, E1_Disable, E2_Disable
inputs D0, D1, D2, D3                   !AT Added for minimum pin test.

outputs E1_Outputs, E2_Outputs
outputs E1_D0, E1_D1, E1_D2, E1_D3      !AT Added for minimum pin test.
outputs E2_D0, E2_D1, E2_D2, E2_D3      !AT Added for minimum pin test.

disable E1_Outputs  with E1_Disable  to "0"
disable E2_Outputs  with E2_Disable  to "0"

when    E1_Disable  is  "0"  inactive   E1_Outputs
when    E2_Disable  is  "0"  inactive   E2_Outputs

trace E1_Outputs to   Clock,Write_Enable,Data_Input,Write_Address
trace E1_Outputs to   E1_Read_Address,E1_Disable

trace E2_Outputs to   Clock,Write_Enable,Data_Input,Write_Address
trace E2_Outputs to   E2_Read_Address,E2_Disable

!************************************************************************
!************************************************************************

vector Data_In_0001
     set Data_Input  to "0001"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Data_In_0010
     set Data_Input  to "0010"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Data_In_0100
     set Data_Input  to "0100"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Data_In_1000
     set Data_Input  to "1000"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Data_In_0000
     set Data_Input  to "0000"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Data_In_1111
     set Data_Input  to "1111"
     set Clock       to "0"
     set Write_Enable to "0"
end vector

vector Write_Address_00
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "00"
     set Write_Enable to "1"
end vector

vector Write_Address_00_WE_false
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "00"
     set Write_Enable to "0"
end vector

vector Write_Address_01
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "01"
     set Write_Enable to "1"
end vector

vector Write_Address_10
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "10"
     set Write_Enable to "1"
end vector

vector Write_Address_11
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "11"
     set Write_Enable to "1"
end vector

vector Clock_High_Write
     set Data_Input  to "KKKK"
     set Clock       to "1"
     set Write_Address to "KK"
     set Write_Enable to "K"
end vector

vector Clock_Low_Write
     set Data_Input  to "KKKK"
     set Clock       to "0"
     set Write_Address to "KK"
     set Write_Enable to "K"
end vector

vector E1_Clock_High_Read
     set Clock       to "1"
     set E1_Read_Address to "KK"
end vector

vector E1_Clock_Low_Read
     set Clock       to "0"
     set E1_Read_Address to "KK"
end vector

vector E2_Clock_High_Read
     set Clock       to "1"
     set E2_Read_Address to "KK"
end vector

vector E2_Clock_Low_Read
     set Clock       to "0"
     set E2_Read_Address to "KK"
end vector

vector E1_Read_Address_00
     set Clock       to "0"
     set E1_Read_Address to "00"
     set E1_Disable  to "1"
     set Write_Enable to "0"
end vector

vector E1_Read_Address_01
     set Clock       to "0"
     set E1_Read_Address to "01"
     set E1_Disable  to "1"
     set Write_Enable to "0"
end vector

vector E1_Read_Address_10
     set Clock       to "0"
     set E1_Read_Address to "10"
     set Write_Enable to "0"
     set E1_Disable  to "1"
end vector

vector E1_Read_Address_11
     set Clock       to "0"
     set E1_Read_Address to "11"
     set Write_Enable to "0"
     set E1_Disable to "1"
end vector

vector E2_Read_Address_00
     set Clock       to "0"
     set E2_Read_Address to "00"
     set E2_Disable  to "1"
     set Write_Enable to "0"
end vector

vector E2_Read_Address_01
     set Clock       to "0"
     set E2_Read_Address to "01"
     set E2_Disable  to "1"
     set Write_Enable to "0"
end vector

vector E2_Read_Address_10
     set Clock       to "0"
     set E2_Read_Address to "10"
     set Write_Enable to "0"
     set E2_Disable  to "1"
end vector

vector E2_Read_Address_11
     set Clock       to "0"
     set E2_Read_Address to "11"
     set Write_Enable to "0"
     set E2_Disable to "1"
end vector

vector E1_Output_0001
     set Clock       to "0"
     set E1_Read_Address to "KK"
     set Write_Enable to "0"
     set E1_Disable  to "0"
     set E1_Outputs  to "0001"
end vector

vector E1_Output_0010
     set Clock       to "0"
     set E1_Read_Address to "KK"
     set Write_Enable to "0"
     set E1_Disable  to "0"
     set E1_Outputs  to "0010"
end vector

vector E1_Output_0100
     set Clock       to "0"
     set E1_Read_Address to "KK"
     set Write_Enable to "0"
     set E1_Disable  to "0"
     set E1_Outputs  to "0100"
end vector

vector E1_Output_1000
     set Clock       to "0"
     set E1_Read_Address to "KK"
     set Write_Enable to "0"
     set E1_Disable  to "0"
     set E1_Outputs  to "1000"
end vector

vector E1_Output_1111
     set Clock       to "0"
     set E1_Read_Address to "KK"
     set Write_Enable to "0"
     set E1_Disable  to "0"
     set E1_Outputs  to "1111"
end vector

vector E2_Output_0001
     set Clock       to "0"
     set E2_Read_Address to "KK"
     set Write_Enable to "0"
     set E2_Disable  to "0"
     set E2_Outputs  to "0001"
end vector

vector E2_Output_0010
     set Clock       to "0"
     set E2_Read_Address to "KK"
     set Write_Enable to "0"
     set E2_Disable  to "0"
     set E2_Outputs  to "0010"
end vector

vector E2_Output_0100
     set Clock       to "0"
     set E2_Read_Address to "KK"
     set Write_Enable to "0"
     set E2_Disable  to "0"
     set E2_Outputs  to "0100"
end vector

vector E2_Output_1000
     set Clock       to "0"
     set E2_Read_Address to "KK"
     set Write_Enable to "0"
     set E2_Disable  to "0"
     set E2_Outputs  to "1000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector Data_In_D0_0
     set D0            to "0"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D0_1
     set D0            to "1"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D1_0
     set D1            to "0"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D1_1
     set D1            to "1"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D2_0
     set D2            to "0"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D2_1
     set D2            to "1"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D3_0
     set D3            to "0"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Data_In_D3_1
     set D3            to "1"
     set Clock         to "0"
     set Write_Enable  to "0"
end vector

vector Write_Address_00_D0
     set D0            to "K"
     set Clock         to "0"
     set Write_Address to "00"
     set Write_Enable  to "1"
end vector

vector Write_Address_00_D1
     set D1            to "K"
     set Clock         to "0"
     set Write_Address to "00"
     set Write_Enable  to "1"
end vector

vector Write_Address_00_D2
     set D2            to "K"
     set Clock         to "0"
     set Write_Address to "00"
     set Write_Enable  to "1"
end vector

vector Write_Address_00_D3
     set D3            to "K"
     set Clock         to "0"
     set Write_Address to "00"
     set Write_Enable  to "1"
end vector

vector Clock_High_Write_D0
     set D0            to "K"
     set Clock         to "1"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_Low_Write_D0
     set D0            to "K"
     set Clock         to "0"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_High_Write_D1
     set D1            to "K"
     set Clock         to "1"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_Low_Write_D1
     set D1            to "K"
     set Clock         to "0"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_High_Write_D2
     set D2            to "K"
     set Clock         to "1"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_Low_Write_D2
     set D2            to "K"
     set Clock         to "0"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_High_Write_D3
     set D3            to "K"
     set Clock         to "1"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector Clock_Low_Write_D3
     set D3            to "K"
     set Clock         to "0"
     set Write_Address to "KK"
     set Write_Enable  to "K"
end vector

vector E1_Output_D0_0
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D0         to "0"
end vector

vector E1_Output_D0_1
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D0         to "1"
end vector

vector E1_Output_D1_0
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D1         to "0"
end vector

vector E1_Output_D1_1
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D1         to "1"
end vector

vector E1_Output_D2_0
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D2         to "0"
end vector

vector E1_Output_D2_1
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D2         to "1"
end vector

vector E1_Output_D3_0
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D3         to "0"
end vector

vector E1_Output_D3_1
     set Clock         to "0"
     set E1_Read_Address to "KK"
     set Write_Enable  to "0"
     set E1_Disable    to "0"
     set E1_D3         to "1"
end vector

vector E2_Output_D0_0
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D0         to "0"
end vector

vector E2_Output_D0_1
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D0         to "1"
end vector

vector E2_Output_D1_0
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D1         to "0"
end vector

vector E2_Output_D1_1
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D1         to "1"
end vector

vector E2_Output_D2_0
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D2         to "0"
end vector

vector E2_Output_D2_1
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D2         to "1"
end vector

vector E2_Output_D3_0
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D3         to "0"
end vector

vector E2_Output_D3_1
     set Clock         to "0"
     set E2_Read_Address to "KK"
     set Write_Enable  to "0"
     set E2_Disable    to "0"
     set E2_D3         to "1"
end vector

!************************************************************************
!************************************************************************

!    Device tested as two separate single port 4-by-4 registers.


sub Write_Clock
     execute Clock_High_Write
     execute Clock_Low_Write
end sub

sub E1_Read_Clock
     execute E1_Clock_High_Read
     execute E1_Clock_Low_Read
end sub

sub E2_Read_Clock
     execute E2_Clock_High_Read
     execute E2_Clock_Low_Read
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_Clock" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus.

sub Write_Clock_Dx (Clock_High_Write_Dx, Clock_Low_Write_Dx)
     execute Clock_High_Write_Dx
     execute Clock_Low_Write_Dx
end sub

!************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 Test"
     execute Data_In_D0_0
     execute Write_Address_00_D0
     call Write_Clock_Dx (Clock_High_Write_D0, Clock_Low_Write_D0)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D0_0

     execute Data_In_D0_1
     execute Write_Address_00_D0
     call Write_Clock_Dx (Clock_High_Write_D0, Clock_Low_Write_D0)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D0_1
end unit

unit "awaretest D1 Test"
     execute Data_In_D1_0
     execute Write_Address_00_D1
     call Write_Clock_Dx (Clock_High_Write_D1, Clock_Low_Write_D1)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D1_0

     execute Data_In_D1_1
     execute Write_Address_00_D1
     call Write_Clock_Dx (Clock_High_Write_D1, Clock_Low_Write_D1)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D1_1
end unit

unit "awaretest D2 Test"
     execute Data_In_D2_0
     execute Write_Address_00_D2
     call Write_Clock_Dx (Clock_High_Write_D2, Clock_Low_Write_D2)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D2_0

     execute Data_In_D2_1
     execute Write_Address_00_D2
     call Write_Clock_Dx (Clock_High_Write_D2, Clock_Low_Write_D2)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D2_1
end unit

unit "awaretest D3 Test"
     execute Data_In_D3_0
     execute Write_Address_00_D3
     call Write_Clock_Dx (Clock_High_Write_D3, Clock_Low_Write_D3)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D3_0

     execute Data_In_D3_1
     execute Write_Address_00_D3
     call Write_Clock_Dx (Clock_High_Write_D3, Clock_Low_Write_D3)

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_D3_1
end unit

unit "awaretest D0 Test"
     execute Data_In_D0_0
     execute Write_Address_00_D0
     call Write_Clock_Dx (Clock_High_Write_D0, Clock_Low_Write_D0)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D0_0

     execute Data_In_D0_1
     execute Write_Address_00_D0
     call Write_Clock_Dx (Clock_High_Write_D0, Clock_Low_Write_D0)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D0_1
end unit

unit "awaretest D1 Test"
     execute Data_In_D1_0
     execute Write_Address_00_D1
     call Write_Clock_Dx (Clock_High_Write_D1, Clock_Low_Write_D1)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D1_0

     execute Data_In_D1_1
     execute Write_Address_00_D1
     call Write_Clock_Dx (Clock_High_Write_D1, Clock_Low_Write_D1)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D1_1
end unit

unit "awaretest D2 Test"
     execute Data_In_D2_0
     execute Write_Address_00_D2
     call Write_Clock_Dx (Clock_High_Write_D2, Clock_Low_Write_D2)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D2_0

     execute Data_In_D2_1
     execute Write_Address_00_D2
     call Write_Clock_Dx (Clock_High_Write_D2, Clock_Low_Write_D2)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D2_1
end unit

unit "awaretest D3 Test"
     execute Data_In_D3_0
     execute Write_Address_00_D3
     call Write_Clock_Dx (Clock_High_Write_D3, Clock_Low_Write_D3)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D3_0

     execute Data_In_D3_1
     execute Write_Address_00_D3
     call Write_Clock_Dx (Clock_High_Write_D3, Clock_Low_Write_D3)

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_D3_1
end unit

!****************************************************************

unit "RAM Test"

     execute Data_In_0001
     execute Write_Address_00
     call Write_Clock
     execute Data_In_0010
     execute Write_Address_01
     call Write_Clock
     execute Data_In_0100
     execute Write_Address_10
     call Write_Clock
     execute Data_In_1000
     execute Write_Address_11
     call Write_Clock

     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_0001
     execute E1_Read_Address_01
     call E1_Read_Clock
     execute E1_Output_0010
     execute E1_Read_Address_10
     call E1_Read_Clock
     execute E1_Output_0100
     execute E1_Read_Address_11
     call E1_Read_Clock
     execute E1_Output_1000

     execute E2_Read_Address_00
     call E2_Read_Clock
     execute E2_Output_0001
     execute E2_Read_Address_01
     call E2_Read_Clock
     execute E2_Output_0010
     execute E2_Read_Address_10
     call E2_Read_Clock
     execute E2_Output_0100
     execute E2_Read_Address_11
     call E2_Read_Clock
     execute E2_Output_1000

     execute Data_In_1111
     execute Write_Address_00
     call Write_Clock
     execute Data_In_0000
     execute Write_Address_00_WE_false
     call Write_Clock
     execute E1_Read_Address_00
     call E1_Read_Clock
     execute E1_Output_1111

end unit


!    End of Test