!!!!    6    0    1  991880089  V1560                                         

! Device           : 4031
! Function         : shift_register totem 64-bit_serial-in/out
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1u
receive delay 900n

assign  VDD         to pins 16
assign  VSS         to pins 8

assign  Data_in_1   to pins 15
assign  Data_in_2   to pins 1

assign  Output      to pins 6
assign  Output_bar  to pins 7
assign  Output_delayed  to pins 5
assign  Data_outputs    to pins 6,7,5
assign  D0              to pins 5          !AT Added for minimum pin test.
assign  D1              to pins 7          !AT Added for minimum pin test.
assign  D2              to pins 6          !AT Added for minimum pin test.

assign  Mode_input  to pins 10
assign  Clock_input to pins 2
assign  Clock_output    to pins 9

assign  NC           to pins 3,4,11,12,13,14

family  CMOS

power   VDD, VSS

inputs  Data_in_1, Data_in_2, Clock_input, Mode_input

outputs Output, Output_bar, Output_delayed
outputs Data_outputs, Clock_output
outputs D0, D1, D2              !AT Added for minimum pin test.

outputs limited to 2 at "0", 2 at "1"

nondigital NC

trace Output to  Data_in_1, Data_in_2, Clock_input, Mode_input
trace Output_bar to  Data_in_1, Data_in_2, Clock_input, Mode_input
trace Output_delayed to Data_in_1, Data_in_2, Clock_input, Mode_input

trace Clock_output   to  Clock_input

!*********************************************************************
!*********************************************************************

vector    Clock_high__1
     set  Mode_input          to "0"
     set  Data_in_1           to "k"
     set  Clock_output        to "1"
     set  Clock_input         to "1"
end vector

vector    Clock_high__2
     set  Mode_input          to "1"
     set  Data_in_2           to "k"
     set  Clock_output        to "1"
     set  Clock_input         to "1"
end vector

vector    Clock_high__serial
     set  Mode_input          to "k"
     set  Clock_output        to "1"
     set  Clock_input         to "1"
end vector

vector    Clock_low
     set  Mode_input          to "k"
     set  Clock_output        to "0"
     set  Clock_input         to "0"
end vector

vector    Data_1_high
     set  Mode_input          to "0"
     set  Clock_input         to "0"
     set  Data_in_1           to "1"
end vector

vector    Data_1_low
     set  Mode_input          to "0"
     set  Clock_input         to "0"
     set  Data_in_1           to "0"
end vector

vector    Data_2_high
     set  Mode_input          to "1"
     set  Clock_input         to "0"
     set  Data_in_2           to "1"
end vector

vector    Data_2_low
     set  Mode_input          to "1"
     set  Clock_input         to "0"
     set  Data_in_2           to "0"
end vector

vector    Outputs_010
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  Data_outputs        to "010"
end vector

vector    Outputs_101
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  Data_outputs        to "101"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Clk_high
     set  Clock_output        to "1"
     set  Clock_input         to "1"
end vector

vector    Clk_low
     set  Clock_output        to "0"
     set  Clock_input         to "0"
end vector

vector    Clock_high__1_AT
     set  Mode_input          to "0"
     set  Data_in_1           to "k"
     set  Clock_input         to "1"
end vector

vector    Clock_high__2_AT
     set  Mode_input          to "1"
     set  Data_in_2           to "k"
     set  Clock_input         to "1"
end vector

vector    Clock_high__serial_AT
     set  Mode_input          to "k"
     set  Clock_input         to "1"
end vector

vector    Clock_low_AT
     set  Mode_input          to "k"
     set  Clock_input         to "0"
end vector

vector    D0_0
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D0                  to "0"
end vector

vector    D0_1
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D0                  to "1"
end vector

vector    D1_0
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D1                  to "0"
end vector

vector    D1_1
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D1                  to "1"
end vector

vector    D2_0
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D2                  to "0"
end vector

vector    D2_1
     set  Mode_input          to "k"
     set  Clock_input         to "0"
     set  D2                  to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_high)
     execute   Clock_high
     execute   Clock_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest Clock output Test"
     execute   Clk_low
     execute   Clk_high
end unit

unit "awaretest D0 Data 1 input Test"
     repeat    32 times
          execute   Data_1_high
          execute   Clock_high__1_AT
          execute   Clock_low_AT
          execute   Data_1_low
          execute   Clock_high__1_AT
          execute   Clock_low_AT
     end repeat
     execute   D0_1
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D0_0
end unit

unit "awaretest D1 Data 1 input Test"
     repeat    32 times
          execute   Data_1_high
          execute   Clock_high__1_AT
          execute   Clock_low_AT
          execute   Data_1_low
          execute   Clock_high__1_AT
          execute   Clock_low_AT
     end repeat
     execute   D1_0
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D1_1
end unit

unit "awaretest D2 Data 1 input Test"
     repeat    32 times
          execute   Data_1_high
          execute   Clock_high__1_AT
          execute   Clock_low_AT
          execute   Data_1_low
          execute   Clock_high__1_AT
          execute   Clock_low_AT
     end repeat
     execute   D2_1
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D2_0
end unit

unit "awaretest D0 Data 2 input Test"
     repeat    32 times
          execute   Data_2_high
          execute   Clock_high__2_AT
          execute   Clock_low_AT
          execute   Data_2_low
          execute   Clock_high__2_AT
          execute   Clock_low_AT
     end repeat
     execute   D0_1
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D0_0
end unit

unit "awaretest D1 Data 2 input Test"
     repeat    32 times
          execute   Data_2_high
          execute   Clock_high__2_AT
          execute   Clock_low_AT
          execute   Data_2_low
          execute   Clock_high__2_AT
          execute   Clock_low_AT
     end repeat
     execute   D1_0
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D1_1
end unit

unit "awaretest D2 Data 2 input Test"
     repeat    32 times
          execute   Data_2_high
          execute   Clock_high__2_AT
          execute   Clock_low_AT
          execute   Data_2_low
          execute   Clock_high__2_AT
          execute   Clock_low_AT
     end repeat
     execute   D2_1
     execute   Clock_high__serial_AT
     execute   Clock_low_AT
     execute   D2_0
end unit

!*********************************************************************

unit "test Data 1 input"
     repeat    32 times
          execute   Data_1_high
          call      Clock_cycle (Clock_high__1)
          execute   Data_1_low
          call      Clock_cycle (Clock_high__1)
     end repeat
     execute   Outputs_101
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_010
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_101
end unit

unit "test Data 2 input"
     repeat    32 times
          execute   Data_2_high
          call      Clock_cycle (Clock_high__2)
          execute   Data_2_low
          call      Clock_cycle (Clock_high__2)
     end repeat
     execute   Outputs_101
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_010
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_101
end unit

!    End of test