!!!!    6    0    1  990227217  V2b5f                                         

! Device           : 7411299
! Function         : shift/storage register 3-state 8_bit_directional_universal
! revision         : B.01.00
! safeguard        : standard_acmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

! warning "Pull-ups are required to test high-impedance outputs."

assign   VCC                 to pins 18,19
assign   GND                 to pins 5,6,7,8

assign   Parallel_in_out     to pins 1,2,3,4,9,10,11,12
assign   P_D0                to pins 12  !AT Added for minimum pin test.
assign   P_D1                to pins 11  !AT Added for minimum pin test.
assign   P_D2                to pins 10  !AT Added for minimum pin test.
assign   P_D3                to pins 9   !AT Added for minimum pin test.
assign   P_D4                to pins 4   !AT Added for minimum pin test.
assign   P_D5                to pins 3   !AT Added for minimum pin test.
assign   P_D6                to pins 2   !AT Added for minimum pin test.
assign   P_D7                to pins 1   !AT Added for minimum pin test.

assign   Serial_input_left   to pins 17
assign   Serial_input_right  to pins 16

assign   A_output            to pins 24
assign   H_output            to pins 13

assign   Clock               to pins 15
assign   Clear_bar           to pins 14
assign   Function_select     to pins 22,23
assign   Output_enable_bar   to pins 21,20

family   TTL

power    VCC, GND

inputs   Serial_input_left, Serial_input_right, Clock
inputs   Clear_bar, Function_select, Output_enable_bar

outputs  A_output, H_output

bidirectional  Parallel_in_out
bidirectional  P_D0, P_D1, P_D2, P_D3      !AT Added for minimum pin test.
bidirectional  P_D4, P_D5, P_D6, P_D7      !AT Added for minimum pin test.

when  Output_enable_bar is "1x"  inactive Parallel_in_out
when  Output_enable_bar is "x1"  inactive Parallel_in_out

when Function_select is "11" inputs Parallel_in_out
when Function_select is "01" outputs Parallel_in_out
when Function_select is "10" outputs Parallel_in_out
when Function_select is "00" outputs Parallel_in_out

trace A_output to Serial_input_left, Serial_input_right, Clock
trace A_output to Clear_bar, Function_select, Output_enable_bar
trace A_output to Parallel_in_out

trace H_output to Serial_input_left, Serial_input_right, Clock
trace H_output to Clear_bar, Function_select, Output_enable_bar
trace H_output to Parallel_in_out

trace Parallel_in_out to Serial_input_left, Serial_input_right, Clock
trace Parallel_in_out to Clear_bar, Function_select, Output_enable_bar

disable Parallel_in_out  with Output_enable_bar  to "1X"
disable Parallel_in_out  with Output_enable_bar  to "X1"

!**************************************************************
!**************************************************************

vector  Clear_low
   receive  Parallel_in_out
   set   Clock                to "0"
   set   Function_select      to "kk"
   set   Output_enable_bar    to "00"
   set   Clear_bar            to "0"
   set   Parallel_in_out      to "00000000"
   set   A_output             to "0"
   set   H_output             to "0"
end vector

vector  Clear_low_load
   set   Clock                to "0"
   set   Function_select      to "kk"
   set   Output_enable_bar    to "00"
   set   Clear_bar            to "0"
   set   A_output             to "0"
   set   H_output             to "0"
end vector

vector  Clock_high__hold
   drive Parallel_in_out
   set   Clear_bar            to "1"
   set   Function_select      to "00"
   set   Parallel_in_out      to "kkkkkkkk"
   set   Clock                to "1"
end vector

vector  Clock_high__load
   drive Parallel_in_out
   set   Clear_bar            to "1"
   set   Function_select      to "11"
   set   Parallel_in_out      to "kkkkkkkk"
   set   Clock                to "1"
end vector

vector  Clock_high__serial_left
   set   Clear_bar            to "1"
   set   Function_select      to "10"
   set   Serial_input_left    to "k"
   set   Clock                to "1"
end vector

vector  Clock_high__serial_right
   set   Clear_bar            to "1"
   set   Function_select      to "01"
   set   Serial_input_right   to "k"
   set   Clock                to "1"
end vector

vector  Clock_high__shift
   set   Clear_bar            to "1"
   set   Function_select      to "kk"
   set   Clock                to "1"
end vector

vector  Clock_low
   set   Clear_bar            to "1"
   set   Function_select      to "kk"
   set   Clock                to "0"
end vector

vector  Function_00
   set   Clear_bar            to "1"
   set   Function_select      to "00"
   set   Clock                to "0"
end vector

vector  Function_01
   set   Clear_bar            to "1"
   set   Function_select      to "01"
   set   Clock                to "0"
end vector

vector  Function_10
   set   Clear_bar            to "1"
   set   Function_select      to "10"
   set   Clock                to "0"
end vector

vector  Outputs_01010101_01
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "01010101"
   set   A_output             to "0"
   set   H_output             to "1"
end vector

vector  Outputs_01010101_01_ksd_right
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   Parallel_in_out      to "01010101"
   set   A_output             to "0"
   set   H_output             to "1"
end vector

vector  Outputs_01010101_01_ksd_left
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   Parallel_in_out      to "01010101"
   set   A_output             to "0"
   set   H_output             to "1"
end vector

vector  Outputs_010101XX_0X
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "010101XX"
   set   A_output             to "0"
end vector

vector  Outputs_10101010_10
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "10101010"
   set   A_output             to "1"
   set   H_output             to "0"
end vector

vector  Outputs_10101010_10_ksd_right
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   Parallel_in_out      to "10101010"
   set   A_output             to "1"
   set   H_output             to "0"
end vector

vector  Outputs_10101010_10_ksd_left
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   Parallel_in_out      to "10101010"
   set   A_output             to "1"
   set   H_output             to "0"
end vector

vector  Outputs_1010101X_1X
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "1010101X"
   set   A_output             to "1"
end vector

vector  Outputs_X0101010_X0
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "X0101010"
   set   H_output             to "0"
end vector

vector  Outputs_XX010101_X1
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "XX010101"
   set   H_output             to "1"
end vector

vector  Outputs_11111111_11
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Parallel_in_out      to "11111111"
   set   A_output             to "1"
   set   H_output             to "1"
end vector

vector  Outputs_11111111_11_ksd_right
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   Parallel_in_out      to "11111111"
   set   A_output             to "1"
   set   H_output             to "1"
end vector

vector  Outputs_11111111_11_ksd_left
   receive  Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   Parallel_in_out      to "11111111"
   set   A_output             to "1"
   set   H_output             to "1"
end vector

vector  Parallel_input_01010101
   drive Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "11"
   set   Parallel_in_out      to "01010101"
end vector

vector  Parallel_input_10101010
   drive Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "11"
   set   Parallel_in_out      to "10101010"
end vector

vector  Parallel_input_11111111
   drive Parallel_in_out
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "11"
   set   Parallel_in_out      to "11111111"
end vector

vector  Serial_input_left_high
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "10"
   set   Serial_input_left    to "1"
end vector

vector  Serial_input_left_low
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "10"
   set   Serial_input_left    to "0"
end vector

vector  Serial_input_right_high
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "01"
   set   Serial_input_right   to "1"
end vector

vector  Serial_input_right_low
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Function_select      to "01"
   set   Serial_input_right   to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  Outputs_P_D0_0_ksd_right
   receive  P_D0
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D0                 to "0"
end vector

vector  Outputs_P_D0_1_ksd_right
   receive  P_D0
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D0                 to "1"
end vector

vector  Outputs_P_D1_0_ksd_right
   receive  P_D1
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D1                 to "0"
end vector

vector  Outputs_P_D1_1_ksd_right
   receive  P_D1
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D1                 to "1"
end vector

vector  Outputs_P_D2_0_ksd_right
   receive  P_D2
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D2                 to "0"
end vector

vector  Outputs_P_D2_1_ksd_right
   receive  P_D2
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D2                 to "1"
end vector

vector  Outputs_P_D3_0_ksd_right
   receive  P_D3
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D3                 to "0"
end vector

vector  Outputs_P_D3_1_ksd_right
   receive  P_D3
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D3                 to "1"
end vector

vector  Outputs_P_D4_0_ksd_right
   receive  P_D4
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D4                 to "0"
end vector

vector  Outputs_P_D4_1_ksd_right
   receive  P_D4
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D4                 to "1"
end vector

vector  Outputs_P_D5_0_ksd_right
   receive  P_D5
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D5                 to "0"
end vector

vector  Outputs_P_D5_1_ksd_right
   receive  P_D5
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D5                 to "1"
end vector

vector  Outputs_P_D6_0_ksd_right
   receive  P_D6
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D6                 to "0"
end vector

vector  Outputs_P_D6_1_ksd_right
   receive  P_D6
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D6                 to "1"
end vector

vector  Outputs_P_D7_0_ksd_right
   receive  P_D7
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D7                 to "0"
end vector

vector  Outputs_P_D7_1_ksd_right
   receive  P_D7
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   P_D7                 to "1"
end vector

vector  Outputs_A_1_ksd_right
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   A_output             to "1"
end vector

vector  Outputs_A_0_ksd_right
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   A_output             to "0"
end vector

vector  Outputs_H_0_ksd_right
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   H_output             to "0"
end vector

vector  Outputs_H_1_ksd_right
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_right   to "k"
   set   H_output             to "1"
end vector

vector  Outputs_P_D0_0_ksd_left
   receive  P_D0
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D0                 to "0"
end vector

vector  Outputs_P_D0_1_ksd_left
   receive  P_D0
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D0                 to "1"
end vector

vector  Outputs_P_D1_0_ksd_left
   receive  P_D1
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D1                 to "0"
end vector

vector  Outputs_P_D1_1_ksd_left
   receive  P_D1
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D1                 to "1"
end vector

vector  Outputs_P_D2_0_ksd_left
   receive  P_D2
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D2                 to "0"
end vector

vector  Outputs_P_D2_1_ksd_left
   receive  P_D2
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D2                 to "1"
end vector

vector  Outputs_P_D3_0_ksd_left
   receive  P_D3
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D3                 to "0"
end vector

vector  Outputs_P_D3_1_ksd_left
   receive  P_D3
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D3                 to "1"
end vector

vector  Outputs_P_D4_0_ksd_left
   receive  P_D4
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D4                 to "0"
end vector

vector  Outputs_P_D4_1_ksd_left
   receive  P_D4
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D4                 to "1"
end vector

vector  Outputs_P_D5_0_ksd_left
   receive  P_D5
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D5                 to "0"
end vector

vector  Outputs_P_D5_1_ksd_left
   receive  P_D5
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D5                 to "1"
end vector

vector  Outputs_P_D6_0_ksd_left
   receive  P_D6
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D6                 to "0"
end vector

vector  Outputs_P_D6_1_ksd_left
   receive  P_D6
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D6                 to "1"
end vector

vector  Outputs_P_D7_0_ksd_left
   receive  P_D7
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D7                 to "0"
end vector

vector  Outputs_P_D7_1_ksd_left
   receive  P_D7
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   P_D7                 to "1"
end vector

vector  Outputs_A_1_ksd_left
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   A_output             to "1"
end vector

vector  Outputs_A_0_ksd_left
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   A_output             to "0"
end vector

vector  Outputs_H_0_ksd_left
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   H_output             to "0"
end vector

vector  Outputs_H_1_ksd_left
   set   Clear_bar            to "1"
   set   Clock                to "0"
   set   Output_enable_bar    to "00"
   set   Function_select      to "kk"
   set   Serial_input_left    to "k"
   set   H_output             to "1"
end vector

!**************************************************************
!**************************************************************

sub  Clock_cycle (Clock_high)
   execute  Clock_high
   execute  Clock_low
end sub

!*************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with P_D0.

unit "awaretest serial input right P_D0 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D0_0_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D0_1_ksd_right
end unit

unit "awaretest serial input right P_D1 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D1_1_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D1_0_ksd_right
end unit

unit "awaretest serial input right P_D2 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D2_0_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D2_1_ksd_right
end unit

unit "awaretest serial input right P_D3 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D3_1_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D3_0_ksd_right
end unit

unit "awaretest serial input right P_D4 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D4_0_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D4_1_ksd_right
end unit

unit "awaretest serial input right P_D5 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D5_1_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D5_0_ksd_right
end unit

unit "awaretest serial input right P_D6 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D6_0_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D6_1_ksd_right
end unit

unit "awaretest serial input right P_D7 Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_P_D7_1_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_P_D7_0_ksd_right
end unit

unit "awaretest serial input right A Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_A_1_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_A_0_ksd_right
end unit

unit "awaretest serial input right H Test"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_H_0_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_H_1_ksd_right
end unit

unit "awaretest serial input left P_D0 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D0_1_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D0_0_ksd_left
end unit

unit "awaretest serial input left P_D1 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D1_0_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D1_1_ksd_left
end unit

unit "awaretest serial input left P_D2 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D2_1_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D2_0_ksd_left
end unit

unit "awaretest serial input left P_D3 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D3_0_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D3_1_ksd_left
end unit

unit "awaretest serial input left P_D4 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D4_1_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D4_0_ksd_left
end unit

unit "awaretest serial input left P_D5 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D5_0_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D5_1_ksd_left
end unit

unit "awaretest serial input left P_D6 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D6_1_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D6_0_ksd_left
end unit

unit "awaretest serial input left P_D7 Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_P_D7_0_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_P_D7_1_ksd_left
end unit

unit "awaretest serial input left A Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_A_0_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_A_1_ksd_left
end unit

unit "awaretest serial input left H Test"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_H_1_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_H_0_ksd_left
end unit


unit  "serial input right"
   repeat   4 times
      execute  Serial_input_right_low
      call  Clock_cycle (Clock_high__serial_right)
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_10101010_10_ksd_right
   execute  Serial_input_right_low
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_01010101_01_ksd_right
   execute  Serial_input_right_high
   call  Clock_cycle (Clock_high__serial_right)
   execute  Outputs_10101010_10_ksd_right
end unit

unit  "serial input left"
   repeat   4 times
      execute  Serial_input_left_low
      call  Clock_cycle (Clock_high__serial_left)
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_01010101_01_ksd_left
   execute  Serial_input_left_low
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_10101010_10_ksd_left
   execute  Serial_input_left_high
   call  Clock_cycle (Clock_high__serial_left)
   execute  Outputs_01010101_01_ksd_left
end unit

unit  "parallel input, shift right"
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_10101010_10
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_01010101_01
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_X0101010_X0
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_XX010101_X1
end unit

unit  "parallel input, shift left"
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_10101010_10
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_01010101_01
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_1010101X_1X
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_010101XX_0X
end unit

unit  "parallel load and hold"
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_00
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Function_00
   execute  Outputs_10101010_10
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_00
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_10101010_10
end unit

unit  "test clear, shift right available"
   repeat   8 times
      execute  Serial_input_right_high
      call  Clock_cycle (Clock_high__serial_right)
   end repeat
   execute  Outputs_11111111_11_ksd_right
   execute  Clear_low
end unit

unit  "test clear, shift left available"
   repeat   8 times
      execute  Serial_input_left_high
      call  Clock_cycle (Clock_high__serial_left)
   end repeat
   execute  Outputs_11111111_11_ksd_left
   execute  Clear_low
end unit

unit  "test clear, parallel inputs"
   execute  Parallel_input_11111111
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_11111111_11
   execute  Clear_low_load
end unit

unit  "circular shift right"
   tied  Serial_input_right, H_output
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_10101010_10
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_01
   execute  Outputs_01010101_01
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_10101010_10
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_01010101_01
end unit

unit  "circular shift left"
   tied  Serial_input_left, A_output
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_01010101_01
   execute  Parallel_input_10101010
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_10101010_10
   execute  Parallel_input_01010101
   call  Clock_cycle (Clock_high__load)
   execute  Function_10
   execute  Outputs_01010101_01
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_10101010_10
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_01010101_01
end unit

!  End of test