!!!!    6    0    1  991860520  V1bca                                         

! Device           : 40104
! Function         : shift_register 3-state 4-bit_bidirectional_universal
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 1u
receive delay 900n

assign  VDD         to pins 16
assign  VSS         to pins 8

assign  Parallel_inputs  to pins 3,4,5,6
assign  Serial_right     to pins 2
assign  Serial_left      to pins 7

assign  Outputs     to pins 15,14,13,12
assign  D0          to pins 12         !AT Added for minimum pin test.
assign  D1          to pins 13         !AT Added for minimum pin test.
assign  D2          to pins 14         !AT Added for minimum pin test.
assign  D3          to pins 15         !AT Added for minimum pin test.

assign  QD_output   to pins 12
assign  QA_output   to pins 15

assign  Clock       to pins 11
assign  Output_enable   to pins 1
assign  Mode_inputs to pins 10,9

family  CMOS

power   VDD, VSS

inputs  Parallel_inputs, Serial_right, Serial_left, Clock
inputs  Output_enable, Mode_inputs

outputs Outputs, QD_output, QA_output
outputs D0, D1, D2, D3          !AT Added for minimum pin test.

disable Outputs with Output_enable to "0"

when  Output_enable is "0" inactive Outputs

trace Outputs to  Parallel_inputs,Serial_right,Serial_left
trace Outputs to  Clock,Output_enable,Mode_inputs

!*********************************************************************
!*********************************************************************

vector    Clock_high__hold
     set  Parallel_inputs     to "kkkk"
     set  Mode_inputs         to "00"
     set  Clock               to "1"
end vector

vector    Clock_high__left
     set  Mode_inputs         to "10"
     set  Serial_left         to "k"
     set  Clock               to "1"
end vector

vector    Clock_high__load
     set  Mode_inputs         to "11"
     set  Parallel_inputs     to "kkkk"
     set  Clock               to "1"
end vector

vector    Clock_high__right
     set  Mode_inputs         to "01"
     set  Serial_right        to "k"
     set  Clock               to "1"
end vector

vector    Clock_high__shift
     set  Mode_inputs         to "kk"
     set  Clock               to "1"
end vector

vector    Clock_low
     set  Mode_inputs         to "kk"
     set  Clock               to "0"
end vector

vector    Inputs_0000
     set  Clock               to "0"
     set  Mode_inputs         to "11"
     set  Parallel_inputs     to "0000"
end vector

vector    Inputs_0000__hold
     set  Clock               to "0"
     set  Mode_inputs         to "00"
     set  Parallel_inputs     to "0000"
end vector

vector    Inputs_0101
     set  Clock               to "0"
     set  Mode_inputs         to "11"
     set  Parallel_inputs     to "0101"
end vector

vector    Inputs_1010
     set  Clock               to "0"
     set  Mode_inputs         to "11"
     set  Parallel_inputs     to "1010"
end vector

vector    Inputs_1111
     set  Clock               to "0"
     set  Mode_inputs         to "11"
     set  Parallel_inputs     to "1111"
end vector

vector    Mode_shift_left
     set  Clock               to "0"
     set  Mode_inputs         to "10"
end vector

vector    Mode_shift_right
     set  Clock               to "0"
     set  Mode_inputs         to "01"
end vector

vector    Outputs_0000
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "0000"
end vector

vector    Outputs_0101
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "0101"
end vector

vector    Outputs_0101_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  Outputs             to "0101"
end vector

vector    Outputs_0101_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  Outputs             to "0101"
end vector

vector    Outputs_010X
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "010X"
end vector

vector    Outputs_01XX
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "01XX"
end vector

vector    Outputs_0XXX
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "0XXX"
end vector

vector    Outputs_1010
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "1010"
end vector

vector    Outputs_1010_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  Outputs             to "1010"
end vector

vector    Outputs_1010_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  Outputs             to "1010"
end vector

vector    Outputs_101X
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "101X"
end vector

vector    Outputs_10XX
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "10XX"
end vector

vector    Outputs_1111
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "1111"
end vector

vector    Outputs_1XXX
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "1XXX"
end vector

vector    Outputs_X010
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "X010"
end vector

vector    Outputs_X101
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "X101"
end vector

vector    Outputs_XX01
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "XX01"
end vector

vector    Outputs_XX10
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "XX10"
end vector

vector    Outputs_XXX0
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "XXX0"
end vector

vector    Outputs_XXX1
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Outputs             to "XXX1"
end vector

vector    Serial_left_high
     set  Clock               to "0"
     set  Mode_inputs         to "10"
     set  Serial_left         to "1"
end vector

vector    Serial_left_low
     set  Clock               to "0"
     set  Mode_inputs         to "10"
     set  Serial_left         to "0"
end vector

vector    Serial_right_high
     set  Clock               to "0"
     set  Mode_inputs         to "01"
     set  Serial_right        to "1"
end vector

vector    Serial_right_low
     set  Clock               to "0"
     set  Mode_inputs         to "01"
     set  Serial_right        to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    D0_0
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D0                  to "0"
end vector

vector    D0_1
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D0                  to "1"
end vector

vector    D1_0
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D1                  to "0"
end vector

vector    D1_1
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D1                  to "1"
end vector

vector    D2_0
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D2                  to "0"
end vector

vector    D2_1
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D2                  to "1"
end vector

vector    D3_0
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D3                  to "0"
end vector

vector    D3_1
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  D3                  to "1"
end vector

vector    D0_0_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D0                  to "0"
end vector

vector    D0_1_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D0                  to "1"
end vector

vector    D1_0_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D1                  to "0"
end vector

vector    D1_1_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D1                  to "1"
end vector

vector    D2_0_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D2                  to "0"
end vector

vector    D2_1_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D2                  to "1"
end vector

vector    D3_0_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D3                  to "0"
end vector

vector    D3_1_ksd_right
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_right        to "k"
     set  D3                  to "1"
end vector

vector    D0_0_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D0                  to "0"
end vector

vector    D0_1_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D0                  to "1"
end vector

vector    D1_0_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D1                  to "0"
end vector

vector    D1_1_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D1                  to "1"
end vector

vector    D2_0_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D2                  to "0"
end vector

vector    D2_1_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D2                  to "1"
end vector

vector    D3_0_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D3                  to "0"
end vector

vector    D3_1_ksd_left
     set  Output_enable       to "1"
     set  Clock               to "0"
     set  Mode_inputs         to "kk"
     set  Serial_left         to "k"
     set  D3                  to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_high)
     execute   Clock_high
     execute   Clock_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 shift right Test"
     repeat    4 times
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D0_0_ksd_right

     repeat    4 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D0_1_ksd_right
end unit

unit "awaretest D1 shift right Test"
     repeat    4 times
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D1_0_ksd_right

     repeat    4 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D1_1_ksd_right
end unit

unit "awaretest D2 shift right Test"
     repeat    4 times
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D2_0_ksd_right

     repeat    4 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D2_1_ksd_right
end unit

unit "awaretest D3 shift right Test"
     repeat    4 times
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D3_0_ksd_right

     repeat    4 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   D3_1_ksd_right
end unit

unit "awaretest D0 shift left Test"
     repeat    4 times
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D0_0_ksd_left

     repeat    4 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D0_1_ksd_left
end unit

unit "awaretest D1 shift left Test"
     repeat    4 times
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D1_0_ksd_left

     repeat    4 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D1_1_ksd_left
end unit

unit "awaretest D2 shift left Test"
     repeat    4 times
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D2_0_ksd_left

     repeat    4 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D2_1_ksd_left
end unit

unit "awaretest D3 shift left Test"
     repeat    4 times
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D3_0_ksd_left

     repeat    4 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   D3_1_ksd_left
end unit

unit "awaretest D0 parallel load Test"
     execute   Inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D0_0
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D0_1
end unit

unit "awaretest D1 parallel load Test"
     execute   Inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D1_0
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D1_1
end unit

unit "awaretest D2 parallel load Test"
     execute   Inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D2_0
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D2_1
end unit

unit "awaretest D3 parallel load Test"
     execute   Inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   D3_0
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   D3_1
end unit

!*********************************************************************

unit "shift right only"
     repeat    2 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
     end repeat
     execute   Outputs_0101_ksd_right
     repeat    2 times
          execute   Serial_right_high
          call      Clock_cycle (Clock_high__right)
          execute   Outputs_1010_ksd_right
          execute   Serial_right_low
          call      Clock_cycle (Clock_high__right)
          execute   Outputs_0101_ksd_right
     end repeat
end unit

unit "shift left only"
     repeat    2 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
     end repeat
     execute   Outputs_1010_ksd_left
     repeat    2 times
          execute   Serial_left_high
          call      Clock_cycle (Clock_high__left)
          execute   Outputs_0101_ksd_left
          execute   Serial_left_low
          call      Clock_cycle (Clock_high__left)
          execute   Outputs_1010_ksd_left
     end repeat
end unit

unit "parallel load and hold"
     execute   Inputs_0000
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0000
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1111
     execute   Inputs_0000__hold
     call      Clock_cycle (Clock_high__hold)
     execute   Outputs_1111
end unit

unit "parallel input, shift right"
     execute   Inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010
     execute   Mode_shift_right
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X101
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX10
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX1
     execute   Inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101
     execute   Mode_shift_right
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X010
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX01
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX0
end unit

unit "parallel input, shift left"
     execute   Inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010
     execute   Mode_shift_left
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_010X
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_10XX
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_0XXX
     execute   Inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101
     execute   Mode_shift_left
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_101X
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_01XX
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_1XXX
end unit

unit "circular shift right, QD and Serial_right tied"
     tied      Serial_right, QD_output
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1111
     execute   Inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010
     execute   Mode_shift_right
     repeat    2 times
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0101
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1010
     end repeat
     execute   Inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101
     execute   Mode_shift_right
     repeat    2 times
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1010
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0101
     end repeat
end unit

unit "circular shift left, QA and Serial_left tied"
     tied      Serial_left, QA_output
     execute   Inputs_1111
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1111
     execute   Inputs_1010
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_1010
     execute   Mode_shift_left
     repeat    2 times
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0101
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1010
     end repeat
     execute   Inputs_0101
     call      Clock_cycle (Clock_high__load)
     execute   Outputs_0101
     execute   Mode_shift_left
     repeat    2 times
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1010
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0101
     end repeat
end unit

!    End of test