!!!!    6    0    1  991663259  V787e                                         

!  $Log: <@(#) A.10.00  New library.> $

!-----------------------------------------------------------------------
!  Copyright (c) Hewlett-Packard Co. 1996
!
!  All Rights Reserved.  Reproduction, adaptation, or translation
!  without prior written permission is prohibited, except as allowed
!  under the copyright laws.
!
!-----------------------------------------------------------------------
!
! Device           : 74f757
! Function         : Octal buffer
! revision         : B.01.00
! safeguard        : high_out_fttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

! Manufacturer  : PHILIPS
! Package       : DIP
! Test Platform : HP3070
!
!-----------------------------------------------------------------------
!
! Additional Information.
!
!       1.     Chip Marking:
!                           74F757N
!                           FSQ6572
!                           9505nC
!       2.     Ordering Information:
!                       Part Number             Package
!                       74F757N                 DIP
!                       74F756D                 SOL
!------------------------------------------------------------------------------

combinatorial

vector cycle 700n
receive delay 600n

assign   VCC         to pins  20
assign   GND         to pins  10

assign   Ia_I        to pins   2,  4,  6,  8
assign   D0a_I       to pins   8            !AT Added for minimum pin test.
assign   D1a_I       to pins   6            !AT Added for minimum pin test.
assign   D2a_I       to pins   4            !AT Added for minimum pin test.
assign   D3a_I       to pins   2            !AT Added for minimum pin test.

assign   Ib_I        to pins  17, 15, 13, 11
assign   D0b_I       to pins  11            !AT Added for minimum pin test.
assign   D1b_I       to pins  13            !AT Added for minimum pin test.
assign   D2b_I       to pins  15            !AT Added for minimum pin test.
assign   D3b_I       to pins  17            !AT Added for minimum pin test.

assign   OEa_bar_I   to pins   1
assign   OEb_I       to pins  19

assign   Ya_O        to pins  18, 16, 14, 12
assign   D0a_O       to pins  12            !AT Added for minimum pin test.
assign   D1a_O       to pins  14            !AT Added for minimum pin test.
assign   D2a_O       to pins  16            !AT Added for minimum pin test.
assign   D3a_O       to pins  18            !AT Added for minimum pin test.

assign   Yb_O        to pins   3,  5,  7,  9
assign   D0b_O       to pins   9            !AT Added for minimum pin test.
assign   D1b_O       to pins   7            !AT Added for minimum pin test.
assign   D2b_O       to pins   5            !AT Added for minimum pin test.
assign   D3b_O       to pins   3            !AT Added for minimum pin test.

family   TTL

format hexadecimal   Ia_I, Ib_I, Ya_O, Yb_O

power    VCC, GND

inputs   Ia_I, Ib_I, OEa_bar_I
inputs   OEb_I
inputs   D0a_I, D1a_I, D2a_I, D3a_I       !AT Added for minimum pin test.
inputs   D0b_I, D1b_I, D2b_I, D3b_I       !AT Added for minimum pin test.

outputs  Ya_O, Yb_O
outputs  D0a_O, D1a_O, D2a_O, D3a_O   !AT Added for minimum pin test.
outputs  D0b_O, D1b_O, D2b_O, D3b_O   !AT Added for minimum pin test.

set load on groups Ya_O, Yb_O to pull up

!
!-----------------------------------------------------------------------
!

vector  Initialize_Inputs
   set   Ia_I        to "0"
   set   Ib_I        to "0"
   set   OEa_bar_I   to "0"
   set   OEb_I       to "1"
end vector

vector  Ia_I_0
   set   OEa_bar_I   to "0"
   set   Ia_I        to "0"
   set   Ya_O        to "0"
end vector

vector  Ia_I_0_OE_Test
   set   OEa_bar_I   to "1"
   set   Ia_I        to "0"
   set   Ya_O        to "F"
end vector

vector  Ia_I_5
   set   OEa_bar_I   to "0"
   set   Ia_I        to "5"
   set   Ya_O        to "5"
end vector

vector  Ia_I_A
   set   OEa_bar_I   to "0"
   set   Ia_I        to "A"
   set   Ya_O        to "A"
end vector

vector  Ia_I_F
   set   OEa_bar_I   to "0"
   set   Ia_I        to "F"
   set   Ya_O        to "F"
end vector

vector  Ib_I_0
   set   OEb_I       to "1"
   set   Ib_I        to "0"
   set   Yb_O        to "X"
   set   Yb_O        to "0"
end vector

vector  Ib_I_0_OEb_Test
   set   OEb_I       to "0"
   set   Ib_I        to "0"
   set   Yb_O        to "F"
end vector

vector  Ib_I_5
   set   OEb_I       to "1"
   set   Ib_I        to "5"
   set   Yb_O        to "5"
end vector

vector  Ib_I_A
   set   OEb_I       to "1"
   set   Ib_I        to "A"
   set   Yb_O        to "A"
end vector

vector  Ib_I_F
   set   OEb_I       to "1"
   set   Ib_I        to "F"
   set   Yb_O        to "F"
end vector

vector  OEa_bar_I_Hi
   set   OEa_bar_I   to "1"
end vector

vector  OEa_bar_I_Lo
   set   OEa_bar_I   to "0"
end vector

vector  OEb_I_Hi
   set   OEb_I       to "1"
end vector

vector  OEb_I_Lo
   set   OEb_I       to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  D0a_I_0
   set   OEa_bar_I   to "0"
   set   D0a_I       to "0"
   set   D0a_O       to "0"
end vector

vector  D0a_I_1
   set   OEa_bar_I   to "0"
   set   D0a_I       to "1"
   set   D0a_O       to "1"
end vector

vector  D1a_I_0
   set   OEa_bar_I   to "0"
   set   D1a_I       to "0"
   set   D1a_O       to "0"
end vector

vector  D1a_I_1
   set   OEa_bar_I   to "0"
   set   D1a_I       to "1"
   set   D1a_O       to "1"
end vector

vector  D2a_I_0
   set   OEa_bar_I   to "0"
   set   D2a_I       to "0"
   set   D2a_O       to "0"
end vector

vector  D2a_I_1
   set   OEa_bar_I   to "0"
   set   D2a_I       to "1"
   set   D2a_O       to "1"
end vector

vector  D3a_I_0
   set   OEa_bar_I   to "0"
   set   D3a_I       to "0"
   set   D3a_O       to "0"
end vector

vector  D3a_I_1
   set   OEa_bar_I   to "0"
   set   D3a_I       to "1"
   set   D3a_O       to "1"
end vector

vector  D0b_I_0
   set   OEb_I       to "1"
   set   D0b_I       to "0"
   set   D0b_O       to "0"
end vector

vector  D0b_I_1
   set   OEb_I       to "1"
   set   D0b_I       to "1"
   set   D0b_O       to "1"
end vector

vector  D1b_I_0
   set   OEb_I       to "1"
   set   D1b_I       to "0"
   set   D1b_O       to "0"
end vector

vector  D1b_I_1
   set   OEb_I       to "1"
   set   D1b_I       to "1"
   set   D1b_O       to "1"
end vector

vector  D2b_I_0
   set   OEb_I       to "1"
   set   D2b_I       to "0"
   set   D2b_O       to "0"
end vector

vector  D2b_I_1
   set   OEb_I       to "1"
   set   D2b_I       to "1"
   set   D2b_O       to "1"
end vector

vector  D3b_I_0
   set   OEb_I       to "1"
   set   D3b_I       to "0"
   set   D3b_O       to "0"
end vector

vector  D3b_I_1
   set   OEb_I       to "1"
   set   D3b_I       to "1"
   set   D3b_O       to "1"
end vector

!
!-----------------------------------------------------------------------
!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0a Test"
   execute  D0a_I_0
   execute  D0a_I_1
end unit

unit "awaretest D1a Test"
   execute  D1a_I_0
   execute  D1a_I_1
end unit

unit "awaretest D2a Test"
   execute  D2a_I_0
   execute  D2a_I_1
end unit

unit "awaretest D3a Test"
   execute  D3a_I_0
   execute  D3a_I_1
end unit

unit "awaretest D0b Test"
   execute  D0b_I_0
   execute  D0b_I_1
end unit

unit "awaretest D1b Test"
   execute  D1b_I_0
   execute  D1b_I_1
end unit

unit "awaretest D2b Test"
   execute  D2b_I_0
   execute  D2b_I_1
end unit

unit "awaretest D3b Test"
   execute  D3b_I_0
   execute  D3b_I_1
end unit


unit  "Test1 : Ia and Ya lines"
   execute  Initialize_Inputs

   execute  Ia_I_0

   execute  Ia_I_5

   execute  Ia_I_A

   execute  Ia_I_A

end unit

unit  "Test2 : OEa line"
   execute  Initialize_inputs
   execute  OEa_bar_I_Lo
   execute  Ia_I_0

   execute  OEa_bar_I_Hi
   execute  Ia_I_0_OE_Test
end unit

unit  "Test3 : Ib and Yb lines"
   execute  Initialize_Inputs

   execute  Ib_I_0

   execute  Ib_I_5

   execute  Ib_I_A

   execute  Ib_I_A

end unit

unit  "Test4 : OEb line"
   execute  Initialize_Inputs

   execute  OEb_I_Hi
   execute  Ib_I_0

   execute  OEb_I_Lo
   execute  Ib_I_0_OEb_Test
end unit

!
!  End of test
!