!!!!    6    0    1  989877910  Vbba9                                         

! Device           : 2804
! Function         : EEPROM 512 x 8
! revision         : B.01.00
! safeguard        : standard_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  1u
receive delay .9u

!  Use pull-downs to test CEbar and OEbar. Pull-ups cannot be used
!  because they affect the programming of the chip. Use 10 - 100 k ohms.
!
warning "Pull-downs are required to test Chip Enable and Output Enable"

assign   VCC            to pins  24
assign   GND            to pins  12

assign   Address        to pins  23,1,2,3,4,5,6,7,8

assign   Data           to pins  17,16,15,14,13,11,10,9
assign   Data_D0        to pins  9    !AT Added for minimum pin test.
assign   Data_D1        to pins  10   !AT Added for minimum pin test.
assign   Data_D2        to pins  11   !AT Added for minimum pin test.
assign   Data_D3        to pins  13   !AT Added for minimum pin test.
assign   Data_D4        to pins  14   !AT Added for minimum pin test.
assign   Data_D5        to pins  15   !AT Added for minimum pin test.
assign   Data_D6        to pins  16   !AT Added for minimum pin test.
assign   Data_D7        to pins  17   !AT Added for minimum pin test.

assign   CEbar          to pins  18
assign   WEbar          to pins  21
assign   OEbar          to pins  20
assign   NC             to pins  22,19

family   TTL

format hexadecimal   Data,Address

power    VCC, GND

inputs   Address,OEbar,CEbar,WEbar

bidirectional  Data
bidirectional Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test.
bidirectional Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test.

nondigital  NC

when     CEbar is "1"   inactive    Data
when     OEbar is "1"   inactive    Data
when     WEbar is "1"   outputs     Data
when     WEbar is "0"   inputs      Data

trace    Data     to    Address,OEbar,CEbar,WEbar

disable  Data  with  CEbar to "1"
disable  Data  with  OEbar to "1"
disable  Data  with  WEbar to "1"

!***************************************************************
!***************************************************************

vector   Initialize
   drive Data
   set   Address        to "000"
   set   Data           to "00"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Keep_inputs
   drive Data
   set   Address        to "kkk"
   set   Data           to "kk"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Do_not_care
   drive Data
   set   Address        to "zzz"
   set   Data           to "zz"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   A_000
   initialize     to Keep_inputs
   set   Address        to "000"
end vector

vector   A_1FF
   initialize     to Keep_inputs
   set   Address        to "1FF"
end vector

vector   D_55D
   initialize     to Keep_inputs
   set   Data           to "55"
end vector

vector   D_AAD
   initialize     to Keep_inputs
   set   Data           to "AA"
end vector

vector   D_55R
   initialize     to Keep_inputs
   receive  Data
   set   Data           to "55"
end vector

vector   D_AAR
   initialize     to Keep_inputs
   receive  Data
   set   Data           to "AA"
end vector

vector   D_00R
   initialize     to Keep_inputs
   receive  Data
   set   Data           to "00"
end vector

vector   CEbar_true
   initialize     to Keep_inputs
   set   CEbar          to "0"
end vector

vector   CEbar_false
   initialize     to Keep_inputs
   set   CEbar          to "1"
end vector

vector   WEbar_true
   initialize     to Keep_inputs
   set   WEbar          to "0"
end vector

vector   WEbar_false
   initialize     to Keep_inputs
   set   WEbar          to "1"
end vector

vector   OEbar_true
   initialize     to Keep_inputs
   set   OEbar          to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Initialize_D0
   drive Data_D0
   set   Address        to "000"
   set   Data_D0        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D1
   drive Data_D1
   set   Address        to "000"
   set   Data_D1        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D2
   drive Data_D2
   set   Address        to "000"
   set   Data_D2        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D3
   drive Data_D3
   set   Address        to "000"
   set   Data_D3        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D4
   drive Data_D4
   set   Address        to "000"
   set   Data_D4        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D5
   drive Data_D5
   set   Address        to "000"
   set   Data_D5        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D6
   drive Data_D6
   set   Address        to "000"
   set   Data_D6        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Initialize_D7
   drive Data_D7
   set   Address        to "000"
   set   Data_D7        to "0"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Keep_inputs_D0
   drive Data_D0
   set   Address        to "kkk"
   set   Data_D0        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D1
   drive Data_D1
   set   Address        to "kkk"
   set   Data_D1        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D2
   drive Data_D2
   set   Address        to "kkk"
   set   Data_D2        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D3
   drive Data_D3
   set   Address        to "kkk"
   set   Data_D3        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D4
   drive Data_D4
   set   Address        to "kkk"
   set   Data_D4        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D5
   drive Data_D5
   set   Address        to "kkk"
   set   Data_D5        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D6
   drive Data_D6
   set   Address        to "kkk"
   set   Data_D6        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Keep_inputs_D7
   drive Data_D7
   set   Address        to "kkk"
   set   Data_D7        to "k"
   set   CEbar          to "k"
   set   OEbar          to "k"
   set   WEbar          to "k"
end vector

vector   Do_not_care_D0
   drive Data_D0
   set   Address        to "zzz"
   set   Data_D0        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D1
   drive Data_D1
   set   Address        to "zzz"
   set   Data_D1        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D2
   drive Data_D2
   set   Address        to "zzz"
   set   Data_D2        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D3
   drive Data_D3
   set   Address        to "zzz"
   set   Data_D3        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D4
   drive Data_D4
   set   Address        to "zzz"
   set   Data_D4        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D5
   drive Data_D5
   set   Address        to "zzz"
   set   Data_D5        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D6
   drive Data_D6
   set   Address        to "zzz"
   set   Data_D6        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   Do_not_care_D7
   drive Data_D7
   set   Address        to "zzz"
   set   Data_D7        to "z"
   set   CEbar          to "1"
   set   OEbar          to "1"
   set   WEbar          to "1"
end vector

vector   A_000_D0
   initialize     to Keep_inputs_D0
   set   Address        to "000"
end vector

vector   A_000_D1
   initialize     to Keep_inputs_D1
   set   Address        to "000"
end vector

vector   A_000_D2
   initialize     to Keep_inputs_D2
   set   Address        to "000"
end vector

vector   A_000_D3
   initialize     to Keep_inputs_D3
   set   Address        to "000"
end vector

vector   A_000_D4
   initialize     to Keep_inputs_D4
   set   Address        to "000"
end vector

vector   A_000_D5
   initialize     to Keep_inputs_D5
   set   Address        to "000"
end vector

vector   A_000_D6
   initialize     to Keep_inputs_D6
   set   Address        to "000"
end vector

vector   A_000_D7
   initialize     to Keep_inputs_D7
   set   Address        to "000"
end vector

vector   D0_0D
   initialize     to Keep_inputs_D0
   set   Data_D0        to "0"
end vector

vector   D0_1D
   initialize     to Keep_inputs_D0
   set   Data_D0        to "1"
end vector

vector   D1_0D
   initialize     to Keep_inputs_D1
   set   Data_D1        to "0"
end vector

vector   D1_1D
   initialize     to Keep_inputs_D1
   set   Data_D1        to "1"
end vector

vector   D2_0D
   initialize     to Keep_inputs_D2
   set   Data_D2        to "0"
end vector

vector   D2_1D
   initialize     to Keep_inputs_D2
   set   Data_D2        to "1"
end vector

vector   D3_0D
   initialize     to Keep_inputs_D3
   set   Data_D3        to "0"
end vector

vector   D3_1D
   initialize     to Keep_inputs_D3
   set   Data_D3        to "1"
end vector

vector   D4_0D
   initialize     to Keep_inputs_D4
   set   Data_D4        to "0"
end vector

vector   D4_1D
   initialize     to Keep_inputs_D4
   set   Data_D4        to "1"
end vector

vector   D5_0D
   initialize     to Keep_inputs_D5
   set   Data_D5        to "0"
end vector

vector   D5_1D
   initialize     to Keep_inputs_D5
   set   Data_D5        to "1"
end vector

vector   D6_0D
   initialize     to Keep_inputs_D6
   set   Data_D6        to "0"
end vector

vector   D6_1D
   initialize     to Keep_inputs_D6
   set   Data_D6        to "1"
end vector

vector   D7_0D
   initialize     to Keep_inputs_D7
   set   Data_D7        to "0"
end vector

vector   D7_1D
   initialize     to Keep_inputs_D7
   set   Data_D7        to "1"
end vector

vector   D0_0R
   initialize     to Keep_inputs_D0
   receive  Data_D0
   set   Data_D0        to "0"
end vector

vector   D0_1R
   initialize     to Keep_inputs_D0
   receive  Data_D0
   set   Data_D0        to "1"
end vector

vector   D1_0R
   initialize     to Keep_inputs_D1
   receive  Data_D1
   set   Data_D1        to "0"
end vector

vector   D1_1R
   initialize     to Keep_inputs_D1
   receive  Data_D1
   set   Data_D1        to "1"
end vector

vector   D2_0R
   initialize     to Keep_inputs_D2
   receive  Data_D2
   set   Data_D2        to "0"
end vector

vector   D2_1R
   initialize     to Keep_inputs_D2
   receive  Data_D2
   set   Data_D2        to "1"
end vector

vector   D3_0R
   initialize     to Keep_inputs_D3
   receive  Data_D3
   set   Data_D3        to "0"
end vector

vector   D3_1R
   initialize     to Keep_inputs_D3
   receive  Data_D3
   set   Data_D3        to "1"
end vector

vector   D4_0R
   initialize     to Keep_inputs_D4
   receive  Data_D4
   set   Data_D4        to "0"
end vector

vector   D4_1R
   initialize     to Keep_inputs_D4
   receive  Data_D4
   set   Data_D4        to "1"
end vector

vector   D5_0R
   initialize     to Keep_inputs_D5
   receive  Data_D5
   set   Data_D5        to "0"
end vector

vector   D5_1R
   initialize     to Keep_inputs_D5
   receive  Data_D5
   set   Data_D5        to "1"
end vector

vector   D6_0R
   initialize     to Keep_inputs_D6
   receive  Data_D6
   set   Data_D6        to "0"
end vector

vector   D6_1R
   initialize     to Keep_inputs_D6
   receive  Data_D6
   set   Data_D6        to "1"
end vector

vector   D7_0R
   initialize     to Keep_inputs_D7
   receive  Data_D7
   set   Data_D7        to "0"
end vector

vector   D7_1R
   initialize     to Keep_inputs_D7
   receive  Data_D7
   set   Data_D7        to "1"
end vector

vector   CEbar_true_D0
   initialize     to Keep_inputs_D0
   set   CEbar          to "0"
end vector

vector   CEbar_false_D0
   initialize     to Keep_inputs_D0
   set   CEbar          to "1"
end vector

vector   WEbar_true_D0
   initialize     to Keep_inputs_D0
   set   WEbar          to "0"
end vector

vector   OEbar_true_D0
   initialize     to Keep_inputs_D0
   set   OEbar          to "0"
end vector

vector   CEbar_true_D1
   initialize     to Keep_inputs_D1
   set   CEbar          to "0"
end vector

vector   CEbar_false_D1
   initialize     to Keep_inputs_D1
   set   CEbar          to "1"
end vector

vector   WEbar_true_D1
   initialize     to Keep_inputs_D1
   set   WEbar          to "0"
end vector

vector   OEbar_true_D1
   initialize     to Keep_inputs_D1
   set   OEbar          to "0"
end vector

vector   CEbar_true_D2
   initialize     to Keep_inputs_D2
   set   CEbar          to "0"
end vector

vector   CEbar_false_D2
   initialize     to Keep_inputs_D2
   set   CEbar          to "1"
end vector

vector   WEbar_true_D2
   initialize     to Keep_inputs_D2
   set   WEbar          to "0"
end vector

vector   OEbar_true_D2
   initialize     to Keep_inputs_D2
   set   OEbar          to "0"
end vector

vector   CEbar_true_D3
   initialize     to Keep_inputs_D3
   set   CEbar          to "0"
end vector

vector   CEbar_false_D3
   initialize     to Keep_inputs_D3
   set   CEbar          to "1"
end vector

vector   WEbar_true_D3
   initialize     to Keep_inputs_D3
   set   WEbar          to "0"
end vector

vector   OEbar_true_D3
   initialize     to Keep_inputs_D3
   set   OEbar          to "0"
end vector

vector   CEbar_true_D4
   initialize     to Keep_inputs_D4
   set   CEbar          to "0"
end vector

vector   CEbar_false_D4
   initialize     to Keep_inputs_D4
   set   CEbar          to "1"
end vector

vector   WEbar_true_D4
   initialize     to Keep_inputs_D4
   set   WEbar          to "0"
end vector

vector   OEbar_true_D4
   initialize     to Keep_inputs_D4
   set   OEbar          to "0"
end vector

vector   CEbar_true_D5
   initialize     to Keep_inputs_D5
   set   CEbar          to "0"
end vector

vector   CEbar_false_D5
   initialize     to Keep_inputs_D5
   set   CEbar          to "1"
end vector

vector   WEbar_true_D5
   initialize     to Keep_inputs_D5
   set   WEbar          to "0"
end vector

vector   OEbar_true_D5
   initialize     to Keep_inputs_D5
   set   OEbar          to "0"
end vector

vector   CEbar_true_D6
   initialize     to Keep_inputs_D6
   set   CEbar          to "0"
end vector

vector   CEbar_false_D6
   initialize     to Keep_inputs_D6
   set   CEbar          to "1"
end vector

vector   WEbar_true_D6
   initialize     to Keep_inputs_D6
   set   WEbar          to "0"
end vector

vector   OEbar_true_D6
   initialize     to Keep_inputs_D6
   set   OEbar          to "0"
end vector

vector   CEbar_true_D7
   initialize     to Keep_inputs_D7
   set   CEbar          to "0"
end vector

vector   CEbar_false_D7
   initialize     to Keep_inputs_D7
   set   CEbar          to "1"
end vector

vector   WEbar_true_D7
   initialize     to Keep_inputs_D7
   set   WEbar          to "0"
end vector

vector   OEbar_true_D7
   initialize     to Keep_inputs_D7
   set   OEbar          to "0"
end vector

!***************************************************************
!***************************************************************

!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"
   execute  Initialize_D0

   execute  A_000_D0
   execute  WEbar_true_D0
   execute  D0_0D
   execute  CEbar_true_D0
   execute  CEbar_false_D0

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
   end repeat

   execute  OEbar_true_D0

   execute  A_000_D0
   execute  CEbar_true_D0
   execute  D0_0R

   execute  Initialize_D0

   execute  A_000_D0
   execute  WEbar_true_D0
   execute  D0_1D
   execute  CEbar_true_D0
   execute  CEbar_false_D0

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
      execute  Do_not_care_D0
   end repeat

   execute  OEbar_true_D0

   execute  A_000_D0
   execute  CEbar_true_D0
   execute  D0_1R

end unit

unit   "awaretest D1 Test"
   execute  Initialize_D1

   execute  A_000_D1
   execute  WEbar_true_D1
   execute  D1_0D
   execute  CEbar_true_D1
   execute  CEbar_false_D1

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
   end repeat

   execute  OEbar_true_D1

   execute  A_000_D1
   execute  CEbar_true_D1
   execute  D1_0R

   execute  Initialize_D1

   execute  A_000_D1
   execute  WEbar_true_D1
   execute  D1_1D
   execute  CEbar_true_D1
   execute  CEbar_false_D1

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
      execute  Do_not_care_D1
   end repeat

   execute  OEbar_true_D1

   execute  A_000_D1
   execute  CEbar_true_D1
   execute  D1_1R

end unit

unit   "awaretest D2 Test"
   execute  Initialize_D2

   execute  A_000_D2
   execute  WEbar_true_D2
   execute  D2_0D
   execute  CEbar_true_D2
   execute  CEbar_false_D2

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
   end repeat

   execute  OEbar_true_D2

   execute  A_000_D2
   execute  CEbar_true_D2
   execute  D2_0R

   execute  Initialize_D2

   execute  A_000_D2
   execute  WEbar_true_D2
   execute  D2_1D
   execute  CEbar_true_D2
   execute  CEbar_false_D2

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
      execute  Do_not_care_D2
   end repeat

   execute  OEbar_true_D2

   execute  A_000_D2
   execute  CEbar_true_D2
   execute  D2_1R

end unit

unit   "awaretest D3 Test"
   execute  Initialize_D3

   execute  A_000_D3
   execute  WEbar_true_D3
   execute  D3_0D
   execute  CEbar_true_D3
   execute  CEbar_false_D3

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
   end repeat

   execute  OEbar_true_D3

   execute  A_000_D3
   execute  CEbar_true_D3
   execute  D3_0R

   execute  Initialize_D3

   execute  A_000_D3
   execute  WEbar_true_D3
   execute  D3_1D
   execute  CEbar_true_D3
   execute  CEbar_false_D3

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
      execute  Do_not_care_D3
   end repeat

   execute  OEbar_true_D3

   execute  A_000_D3
   execute  CEbar_true_D3
   execute  D3_1R

end unit

unit   "awaretest D4 Test"
   execute  Initialize_D4

   execute  A_000_D4
   execute  WEbar_true_D4
   execute  D4_0D
   execute  CEbar_true_D4
   execute  CEbar_false_D4

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
   end repeat

   execute  OEbar_true_D4

   execute  A_000_D4
   execute  CEbar_true_D4
   execute  D4_0R

   execute  Initialize_D4

   execute  A_000_D4
   execute  WEbar_true_D4
   execute  D4_1D
   execute  CEbar_true_D4
   execute  CEbar_false_D4

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
      execute  Do_not_care_D4
   end repeat

   execute  OEbar_true_D4

   execute  A_000_D4
   execute  CEbar_true_D4
   execute  D4_1R

end unit

unit   "awaretest D5 Test"
   execute  Initialize_D5

   execute  A_000_D5
   execute  WEbar_true_D5
   execute  D5_0D
   execute  CEbar_true_D5
   execute  CEbar_false_D5

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
   end repeat

   execute  OEbar_true_D5

   execute  A_000_D5
   execute  CEbar_true_D5
   execute  D5_0R

   execute  Initialize_D5

   execute  A_000_D5
   execute  WEbar_true_D5
   execute  D5_1D
   execute  CEbar_true_D5
   execute  CEbar_false_D5

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
      execute  Do_not_care_D5
   end repeat

   execute  OEbar_true_D5

   execute  A_000_D5
   execute  CEbar_true_D5
   execute  D5_1R

end unit

unit   "awaretest D6 Test"
   execute  Initialize_D6

   execute  A_000_D6
   execute  WEbar_true_D6
   execute  D6_0D
   execute  CEbar_true_D6
   execute  CEbar_false_D6

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
   end repeat

   execute  OEbar_true_D6

   execute  A_000_D6
   execute  CEbar_true_D6
   execute  D6_0R

   execute  Initialize_D6

   execute  A_000_D6
   execute  WEbar_true_D6
   execute  D6_1D
   execute  CEbar_true_D6
   execute  CEbar_false_D6

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
      execute  Do_not_care_D6
   end repeat

   execute  OEbar_true_D6

   execute  A_000_D6
   execute  CEbar_true_D6
   execute  D6_1R

end unit

unit   "awaretest D7 Test"
   execute  Initialize_D7

   execute  A_000_D7
   execute  WEbar_true_D7
   execute  D7_0D
   execute  CEbar_true_D7
   execute  CEbar_false_D7

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
   end repeat

   execute  OEbar_true_D7

   execute  A_000_D7
   execute  CEbar_true_D7
   execute  D7_0R

   execute  Initialize_D7

   execute  A_000_D7
   execute  WEbar_true_D7
   execute  D7_1D
   execute  CEbar_true_D7
   execute  CEbar_false_D7

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
      execute  Do_not_care_D7
   end repeat

   execute  OEbar_true_D7

   execute  A_000_D7
   execute  CEbar_true_D7
   execute  D7_1R

end unit

unit "Program Ram"
   execute  Initialize

   execute  A_000           ! program address 000 to 55H
   execute  WEbar_true
   execute  D_55D
   execute  CEbar_true
   execute  CEbar_false

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
   end repeat

   execute  OEbar_true

   execute  A_000              ! read address 000
   execute  CEbar_true
   execute  D_55R

   execute  Initialize

   execute  A_1FF           ! program address 1FF to AAH
   execute  WEbar_true
   execute  D_AAD
   execute  CEbar_true
   execute  CEbar_false

   repeat 200 times           ! Wait 10 ms.
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
      execute  Do_not_care
   end repeat

   execute  A_1FF              ! read address 1FF
   execute  CEbar_true
   execute  D_AAR
end unit

unit "test CEbar"       ! use 10k pull-downs on data bus for this unit
!! execute  Initialize
!! execute  OEbar_true
!!
!! execute  A_000              ! read address 000
!! execute  D_00R
end unit

unit "test OEbar"       ! use 10k pull-downs on data bus for this unit
!! execute  Initialize
!!
!! execute  A_1FF              ! read address 1FF
!! execute  CEbar_true
!! execute  D_00R
end unit



!    End of test