!!!!    6    0    1  990474744  V1eef                                         

! Device           : 742952
! Function         : 8-Bit Bus Register Transceiver
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!Monolithic Memories Spec. sheet

sequential

vector cycle  2000n
receive delay 1900n

!assignment for PLCC packages

assign VCC            to  pins 28
assign GND            to  pins 14

assign Clk_A          to  pins 12
assign Clk_B          to  pins 17
assign Clk_Enable_A   to  pins 13
assign Clk_Enable_B   to  pins 16
assign OutputA_to_B   to  pins 11
assign OutputB_to_A   to  pins 18
assign Side_A         to  pins 27,26,25,24
assign Side_A         to  pins 23,21,20,19
assign A0             to  pins 19           !AT Added for minimum pin test.
assign A1             to  pins 20           !AT Added for minimum pin test.
assign A2             to  pins 21           !AT Added for minimum pin test.
assign A3             to  pins 23           !AT Added for minimum pin test.
assign A4             to  pins 24           !AT Added for minimum pin test.
assign A5             to  pins 25           !AT Added for minimum pin test.
assign A6             to  pins 26           !AT Added for minimum pin test.
assign A7             to  pins 27           !AT Added for minimum pin test.

assign Side_B         to  pins 2,3,4,5
assign Side_B         to  pins 6,7,9,10
assign B0             to  pins 10           !AT Added for minimum pin test.
assign B1             to  pins 9            !AT Added for minimum pin test.
assign B2             to  pins 7            !AT Added for minimum pin test.
assign B3             to  pins 6            !AT Added for minimum pin test.
assign B4             to  pins 5            !AT Added for minimum pin test.
assign B5             to  pins 4            !AT Added for minimum pin test.
assign B6             to  pins 3            !AT Added for minimum pin test.
assign B7             to  pins 2            !AT Added for minimum pin test.

assign NC             to  pins 1,8,15,22
assign Disable_1      to  pins 12,17,13,16
assign Disable_2      to  pins 13,16

family    TTL
power     VCC,GND

format hexadecimal Side_A,Side_B

nondigital NC

inputs Clk_A,Clk_B,Clk_Enable_A,Clk_Enable_B
inputs OutputA_to_B,OutputB_to_A

bidirectional Side_A,Side_B
bidirectional A0, A1, A2, A3, A4, A5, A6, A7    !AT Added for minimum pin test.
bidirectional B0, B1, B2, B3, B4, B5, B6, B7    !AT Added for minimum pin test.

!*******************   Disable Information   ************************

disable Side_A,Side_B with Disable_1 to "tt11" 5 times

!*******************   Backtrace Information  ***********************

when Disable_2 is "11" inactive Side_A,Side_B
when Disable_2 is "00" inputs Side_A,Side_B
when Disable_2 is "01" inputs Side_A
when Disable_2 is "01" inactive Side_B
when Disable_2 is "10" inputs Side_B
when Disable_2 is "10" inactive Side_A


trace Side_A,Side_B to Clk_A,Clk_B,Clk_Enable_A,Clk_Enable_B
trace Side_A,Side_B to OutputA_to_B,OutputB_to_A

!This test checks all pins. If Clk_Enable_A and Clk_Enable_B are
!tied low, the unit "Test Clock Enable pins" can be commented
!out and the test will check all other pins.
!This program uses the storage mode and the transfer of data from
!A to B and B to A.

!********************************************************************
!               VECTOR DEFINITION SECTION BEGINS
!********************************************************************


vector Set_Values               !Set the device with known values.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set Side_A          to "00"
   set Side_B          to "00"
end vector

vector Save_Values              !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Side_A          to "kk"
   set Side_B          to "kk"
end vector

vector Save_A_Values            !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set Side_A          to "kk"
   set Side_B          to "xx"
end vector

vector Save_B_Values            !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set Side_A          to "xx"
   set Side_B          to "kk"
end vector

vector Clk_A_high               !Clock A and latch values when storing data.
   initialize to Save_Values
   set Clk_A   to "1"
end vector

vector Clk_A_low
   initialize to Save_Values
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high         !Clock A and latch values
   initialize to Save_A_Values  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low
   initialize to Save_A_Values
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high       !Clock A and latch values
   initialize to Save_B_Values  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low
   initialize to Save_B_values
   set Clk_A   to "0"
end vector

vector Clk_B_high               !Latch values when storing data.
   initialize to Save_Values
   set Clk_B   to "1"
end vector

vector Clk_B_low
   initialize to Save_Values
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low          !Clock B and latch values when
   initialize to Save_B_values  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high
   initialize to Save_B_Values
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high       !Clock B and latch values
   initialize to Save_A_Values  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low
   initialize to Save_A_values
   set Clk_B    to "0"
end vector

vector Clk_A_Enable             !Enable clock A when in the storage mode.
   initialize to Save_Values
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive     !Enable clock A when receiving at A.
   initialize to Save_B_values
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive    !Disable clock A when receiving at A.
   initialize to Save_B_Values
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable             !Enable clock B when in storage mode.
   initialize to Save_Values
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive       !Enable clock B when transmitting B to A
   initialize to Save_B_Values
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive       !Enable A to B output.
   initialize to Save_A_Values
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive     !Enable output received by A from B.
   initialize to Save_B_Values
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive       !Enable B to A output.
   initialize to Save_B_Values
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive     !Enable output received by B from A.
   initialize to Save_A_Values
   set OutputB_to_A to "1"
end vector

!**********  The remaining vectors set the data lines.  *************

vector A_to_B_00
   initialize to Save_A_Values
   drive Side_A
   set Side_A to "00"
end vector

vector A_to_B_55
   initialize to Save_A_Values
   drive Side_A
   set Side_A to "55"
end vector

vector Output_B_55
   initialize to Save_A_Values
   receive Side_B
   set Side_B to "55"
end vector

vector A_to_B_AA
   initialize to Save_A_Values
   drive Side_A
   set Side_A to "AA"
end vector

vector Output_B_AA
   initialize to Save_A_Values
   receive Side_B
   set Side_B to "AA"
end vector

vector B_to_A_55
   initialize to Save_B_Values
   drive Side_B
   set Side_B to "55"
end vector

vector B_to_A_00
   initialize to Save_B_Values
   drive Side_B
   set Side_B to "00"
end vector

vector Output_A_55
   initialize to Save_B_Values
   receive Side_A
   set Side_A to "55"
end vector

vector B_to_A_AA
   initialize to Save_B_Values
   drive Side_B
   set Side_B to "AA"
end vector

vector Output_A_AA
   initialize to Save_B_Values
   receive Side_A
   set Side_A to "AA"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the A or B bus was copied and modified to reference
!AT only a single pin of the bus.

vector Set_Values_A0_B0         !Set the device with known values.
   drive A0
   drive B0
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A0              to "0"
   set B0              to "0"
end vector

vector Save_Values_A0_B0        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A0              to "k"
   set B0              to "k"
end vector

vector Save_A_Values_A0_B0      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A0              to "k"
   set B0              to "x"
end vector

vector Save_B_Values_A0_B0      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A0              to "x"
   set B0              to "k"
end vector

vector Clk_A_high_A0_B0            !Clock A and latch values when storing data.
   initialize to Save_Values_A0_B0
   set Clk_A   to "1"
end vector

vector Clk_A_low_A0_B0
   initialize to Save_Values_A0_B0
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A0_B0         !Clock A and latch values
   initialize to Save_A_Values_A0_B0  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A0_B0
   initialize to Save_A_Values_A0_B0
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A0_B0       !Clock A and latch values
   initialize to Save_B_Values_A0_B0  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A0_B0
   initialize to Save_B_Values_A0_B0
   set Clk_A   to "0"
end vector

vector Clk_B_high_A0_B0               !Latch values when storing data.
   initialize to Save_Values_A0_B0
   set Clk_B   to "1"
end vector

vector Clk_B_low_A0_B0
   initialize to Save_Values_A0_B0
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A0_B0          !Clock B and latch values when
   initialize to Save_B_Values_A0_B0  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A0_B0
   initialize to Save_B_Values_A0_B0
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A0_B0       !Clock B and latch values
   initialize to Save_A_Values_A0_B0  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A0_B0
   initialize to Save_A_Values_A0_B0
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A0_B0             !Enable clock A when in the storage mode.
   initialize to Save_Values_A0_B0
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A0_B0       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A0_B0
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A0_B0      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A0_B0
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A0_B0     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A0_B0
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A0_B0    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A0_B0
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A0_B0             !Enable clock B when in storage mode.
   initialize to Save_Values_A0_B0
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A0_B0       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A0_B0
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A0_B0      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A0_B0
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A0_B0     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A0_B0
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A0_B0    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A0_B0
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A0_B0       !Enable A to B output.
   initialize to Save_A_Values_A0_B0
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A0_B0     !Enable output received by A from B.
   initialize to Save_B_Values_A0_B0
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A0_B0       !Enable B to A output.
   initialize to Save_B_Values_A0_B0
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A0_B0     !Enable output received by B from A.
   initialize to Save_A_Values_A0_B0
   set OutputB_to_A to "1"
end vector


vector A0_to_B0_0
   initialize to Save_A_Values_A0_B0
   drive A0
   set A0     to "0"
end vector

vector A0_to_B0_1
   initialize to Save_A_Values_A0_B0
   drive A0
   set A0     to "1"
end vector

vector B0_to_A0_0
   initialize to Save_B_Values_A0_B0
   drive B0
   set B0     to "0"
end vector

vector B0_to_A0_1
   initialize to Save_B_Values_A0_B0
   drive B0
   set B0     to "1"
end vector

vector Output_B0_0
   initialize to Save_A_Values_A0_B0
   receive B0
   set B0     to "0"
end vector

vector Output_B0_1
   initialize to Save_A_Values_A0_B0
   receive B0
   set B0     to "1"
end vector

vector Output_A0_0
   initialize to Save_B_Values_A0_B0
   receive A0
   set A0     to "0"
end vector

vector Output_A0_1
   initialize to Save_B_Values_A0_B0
   receive A0
   set A0     to "1"
end vector

vector Set_Values_A1_B1         !Set the device with known values.
   drive A1
   drive B1
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A1              to "0"
   set B1              to "0"
end vector

vector Save_Values_A1_B1        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A1              to "k"
   set B1              to "k"
end vector

vector Save_A_Values_A1_B1      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A1              to "k"
   set B1              to "x"
end vector

vector Save_B_Values_A1_B1      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A1              to "x"
   set B1              to "k"
end vector

vector Clk_A_high_A1_B1            !Clock A and latch values when storing data.
   initialize to Save_Values_A1_B1
   set Clk_A   to "1"
end vector

vector Clk_A_low_A1_B1
   initialize to Save_Values_A1_B1
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A1_B1         !Clock A and latch values
   initialize to Save_A_Values_A1_B1  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A1_B1
   initialize to Save_A_Values_A1_B1
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A1_B1       !Clock A and latch values
   initialize to Save_B_Values_A1_B1  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A1_B1
   initialize to Save_B_Values_A1_B1
   set Clk_A   to "0"
end vector

vector Clk_B_high_A1_B1               !Latch values when storing data.
   initialize to Save_Values_A1_B1
   set Clk_B   to "1"
end vector

vector Clk_B_low_A1_B1
   initialize to Save_Values_A1_B1
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A1_B1          !Clock B and latch values when
   initialize to Save_B_Values_A1_B1  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A1_B1
   initialize to Save_B_Values_A1_B1
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A1_B1       !Clock B and latch values
   initialize to Save_A_Values_A1_B1  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A1_B1
   initialize to Save_A_Values_A1_B1
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A1_B1             !Enable clock A when in the storage mode.
   initialize to Save_Values_A1_B1
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A1_B1       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A1_B1
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A1_B1      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A1_B1
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A1_B1     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A1_B1
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A1_B1    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A1_B1
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A1_B1             !Enable clock B when in storage mode.
   initialize to Save_Values_A1_B1
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A1_B1       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A1_B1
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A1_B1      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A1_B1
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A1_B1     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A1_B1
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A1_B1    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A1_B1
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A1_B1       !Enable A to B output.
   initialize to Save_A_Values_A1_B1
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A1_B1     !Enable output received by A from B.
   initialize to Save_B_Values_A1_B1
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A1_B1       !Enable B to A output.
   initialize to Save_B_Values_A1_B1
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A1_B1     !Enable output received by B from A.
   initialize to Save_A_Values_A1_B1
   set OutputB_to_A to "1"
end vector


vector A1_to_B1_0
   initialize to Save_A_Values_A1_B1
   drive A1
   set A1     to "0"
end vector

vector A1_to_B1_1
   initialize to Save_A_Values_A1_B1
   drive A1
   set A1     to "1"
end vector

vector B1_to_A1_0
   initialize to Save_B_Values_A1_B1
   drive B1
   set B1     to "0"
end vector

vector B1_to_A1_1
   initialize to Save_B_Values_A1_B1
   drive B1
   set B1     to "1"
end vector

vector Output_B1_0
   initialize to Save_A_Values_A1_B1
   receive B1
   set B1     to "0"
end vector

vector Output_B1_1
   initialize to Save_A_Values_A1_B1
   receive B1
   set B1     to "1"
end vector

vector Output_A1_0
   initialize to Save_B_Values_A1_B1
   receive A1
   set A1     to "0"
end vector

vector Output_A1_1
   initialize to Save_B_Values_A1_B1
   receive A1
   set A1     to "1"
end vector

vector Set_Values_A2_B2         !Set the device with known values.
   drive A2
   drive B2
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A2              to "0"
   set B2              to "0"
end vector

vector Save_Values_A2_B2        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A2              to "k"
   set B2              to "k"
end vector

vector Save_A_Values_A2_B2      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A2              to "k"
   set B2              to "x"
end vector

vector Save_B_Values_A2_B2      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A2              to "x"
   set B2              to "k"
end vector

vector Clk_A_high_A2_B2            !Clock A and latch values when storing data.
   initialize to Save_Values_A2_B2
   set Clk_A   to "1"
end vector

vector Clk_A_low_A2_B2
   initialize to Save_Values_A2_B2
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A2_B2         !Clock A and latch values
   initialize to Save_A_Values_A2_B2  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A2_B2
   initialize to Save_A_Values_A2_B2
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A2_B2       !Clock A and latch values
   initialize to Save_B_Values_A2_B2  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A2_B2
   initialize to Save_B_Values_A2_B2
   set Clk_A   to "0"
end vector

vector Clk_B_high_A2_B2               !Latch values when storing data.
   initialize to Save_Values_A2_B2
   set Clk_B   to "1"
end vector

vector Clk_B_low_A2_B2
   initialize to Save_Values_A2_B2
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A2_B2          !Clock B and latch values when
   initialize to Save_B_Values_A2_B2  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A2_B2
   initialize to Save_B_Values_A2_B2
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A2_B2       !Clock B and latch values
   initialize to Save_A_Values_A2_B2  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A2_B2
   initialize to Save_A_Values_A2_B2
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A2_B2             !Enable clock A when in the storage mode.
   initialize to Save_Values_A2_B2
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A2_B2       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A2_B2
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A2_B2      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A2_B2
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A2_B2     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A2_B2
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A2_B2    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A2_B2
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A2_B2             !Enable clock B when in storage mode.
   initialize to Save_Values_A2_B2
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A2_B2       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A2_B2
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A2_B2      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A2_B2
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A2_B2     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A2_B2
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A2_B2    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A2_B2
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A2_B2       !Enable A to B output.
   initialize to Save_A_Values_A2_B2
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A2_B2     !Enable output received by A from B.
   initialize to Save_B_Values_A2_B2
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A2_B2       !Enable B to A output.
   initialize to Save_B_Values_A2_B2
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A2_B2     !Enable output received by B from A.
   initialize to Save_A_Values_A2_B2
   set OutputB_to_A to "1"
end vector


vector A2_to_B2_0
   initialize to Save_A_Values_A2_B2
   drive A2
   set A2     to "0"
end vector

vector A2_to_B2_1
   initialize to Save_A_Values_A2_B2
   drive A2
   set A2     to "1"
end vector

vector B2_to_A2_0
   initialize to Save_B_Values_A2_B2
   drive B2
   set B2     to "0"
end vector

vector B2_to_A2_1
   initialize to Save_B_Values_A2_B2
   drive B2
   set B2     to "1"
end vector

vector Output_B2_0
   initialize to Save_A_Values_A2_B2
   receive B2
   set B2     to "0"
end vector

vector Output_B2_1
   initialize to Save_A_Values_A2_B2
   receive B2
   set B2     to "1"
end vector

vector Output_A2_0
   initialize to Save_B_Values_A2_B2
   receive A2
   set A2     to "0"
end vector

vector Output_A2_1
   initialize to Save_B_Values_A2_B2
   receive A2
   set A2     to "1"
end vector

vector Set_Values_A3_B3         !Set the device with known values.
   drive A3
   drive B3
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A3              to "0"
   set B3              to "0"
end vector

vector Save_Values_A3_B3        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A3              to "k"
   set B3              to "k"
end vector

vector Save_A_Values_A3_B3      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A3              to "k"
   set B3              to "x"
end vector

vector Save_B_Values_A3_B3      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A3              to "x"
   set B3              to "k"
end vector

vector Clk_A_high_A3_B3            !Clock A and latch values when storing data.
   initialize to Save_Values_A3_B3
   set Clk_A   to "1"
end vector

vector Clk_A_low_A3_B3
   initialize to Save_Values_A3_B3
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A3_B3         !Clock A and latch values
   initialize to Save_A_Values_A3_B3  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A3_B3
   initialize to Save_A_Values_A3_B3
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A3_B3       !Clock A and latch values
   initialize to Save_B_Values_A3_B3  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A3_B3
   initialize to Save_B_Values_A3_B3
   set Clk_A   to "0"
end vector

vector Clk_B_high_A3_B3               !Latch values when storing data.
   initialize to Save_Values_A3_B3
   set Clk_B   to "1"
end vector

vector Clk_B_low_A3_B3
   initialize to Save_Values_A3_B3
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A3_B3          !Clock B and latch values when
   initialize to Save_B_Values_A3_B3  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A3_B3
   initialize to Save_B_Values_A3_B3
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A3_B3       !Clock B and latch values
   initialize to Save_A_Values_A3_B3  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A3_B3
   initialize to Save_A_Values_A3_B3
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A3_B3             !Enable clock A when in the storage mode.
   initialize to Save_Values_A3_B3
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A3_B3       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A3_B3
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A3_B3      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A3_B3
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A3_B3     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A3_B3
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A3_B3    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A3_B3
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A3_B3             !Enable clock B when in storage mode.
   initialize to Save_Values_A3_B3
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A3_B3       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A3_B3
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A3_B3      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A3_B3
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A3_B3     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A3_B3
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A3_B3    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A3_B3
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A3_B3       !Enable A to B output.
   initialize to Save_A_Values_A3_B3
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A3_B3     !Enable output received by A from B.
   initialize to Save_B_Values_A3_B3
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A3_B3       !Enable B to A output.
   initialize to Save_B_Values_A3_B3
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A3_B3     !Enable output received by B from A.
   initialize to Save_A_Values_A3_B3
   set OutputB_to_A to "1"
end vector


vector A3_to_B3_0
   initialize to Save_A_Values_A3_B3
   drive A3
   set A3     to "0"
end vector

vector A3_to_B3_1
   initialize to Save_A_Values_A3_B3
   drive A3
   set A3     to "1"
end vector

vector B3_to_A3_0
   initialize to Save_B_Values_A3_B3
   drive B3
   set B3     to "0"
end vector

vector B3_to_A3_1
   initialize to Save_B_Values_A3_B3
   drive B3
   set B3     to "1"
end vector

vector Output_B3_0
   initialize to Save_A_Values_A3_B3
   receive B3
   set B3     to "0"
end vector

vector Output_B3_1
   initialize to Save_A_Values_A3_B3
   receive B3
   set B3     to "1"
end vector

vector Output_A3_0
   initialize to Save_B_Values_A3_B3
   receive A3
   set A3     to "0"
end vector

vector Output_A3_1
   initialize to Save_B_Values_A3_B3
   receive A3
   set A3     to "1"
end vector

vector Set_Values_A4_B4         !Set the device with known values.
   drive A4
   drive B4
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A4              to "0"
   set B4              to "0"
end vector

vector Save_Values_A4_B4        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A4              to "k"
   set B4              to "k"
end vector

vector Save_A_Values_A4_B4      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A4              to "k"
   set B4              to "x"
end vector

vector Save_B_Values_A4_B4      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A4              to "x"
   set B4              to "k"
end vector

vector Clk_A_high_A4_B4            !Clock A and latch values when storing data.
   initialize to Save_Values_A4_B4
   set Clk_A   to "1"
end vector

vector Clk_A_low_A4_B4
   initialize to Save_Values_A4_B4
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A4_B4         !Clock A and latch values
   initialize to Save_A_Values_A4_B4  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A4_B4
   initialize to Save_A_Values_A4_B4
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A4_B4       !Clock A and latch values
   initialize to Save_B_Values_A4_B4  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A4_B4
   initialize to Save_B_Values_A4_B4
   set Clk_A   to "0"
end vector

vector Clk_B_high_A4_B4               !Latch values when storing data.
   initialize to Save_Values_A4_B4
   set Clk_B   to "1"
end vector

vector Clk_B_low_A4_B4
   initialize to Save_Values_A4_B4
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A4_B4          !Clock B and latch values when
   initialize to Save_B_Values_A4_B4  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A4_B4
   initialize to Save_B_Values_A4_B4
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A4_B4       !Clock B and latch values
   initialize to Save_A_Values_A4_B4  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A4_B4
   initialize to Save_A_Values_A4_B4
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A4_B4             !Enable clock A when in the storage mode.
   initialize to Save_Values_A4_B4
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A4_B4       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A4_B4
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A4_B4      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A4_B4
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A4_B4     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A4_B4
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A4_B4    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A4_B4
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A4_B4             !Enable clock B when in storage mode.
   initialize to Save_Values_A4_B4
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A4_B4       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A4_B4
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A4_B4      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A4_B4
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A4_B4     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A4_B4
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A4_B4    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A4_B4
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A4_B4       !Enable A to B output.
   initialize to Save_A_Values_A4_B4
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A4_B4     !Enable output received by A from B.
   initialize to Save_B_Values_A4_B4
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A4_B4       !Enable B to A output.
   initialize to Save_B_Values_A4_B4
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A4_B4     !Enable output received by B from A.
   initialize to Save_A_Values_A4_B4
   set OutputB_to_A to "1"
end vector


vector A4_to_B4_0
   initialize to Save_A_Values_A4_B4
   drive A4
   set A4     to "0"
end vector

vector A4_to_B4_1
   initialize to Save_A_Values_A4_B4
   drive A4
   set A4     to "1"
end vector

vector B4_to_A4_0
   initialize to Save_B_Values_A4_B4
   drive B4
   set B4     to "0"
end vector

vector B4_to_A4_1
   initialize to Save_B_Values_A4_B4
   drive B4
   set B4     to "1"
end vector

vector Output_B4_0
   initialize to Save_A_Values_A4_B4
   receive B4
   set B4     to "0"
end vector

vector Output_B4_1
   initialize to Save_A_Values_A4_B4
   receive B4
   set B4     to "1"
end vector

vector Output_A4_0
   initialize to Save_B_Values_A4_B4
   receive A4
   set A4     to "0"
end vector

vector Output_A4_1
   initialize to Save_B_Values_A4_B4
   receive A4
   set A4     to "1"
end vector

vector Set_Values_A5_B5         !Set the device with known values.
   drive A5
   drive B5
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A5              to "0"
   set B5              to "0"
end vector

vector Save_Values_A5_B5        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A5              to "k"
   set B5              to "k"
end vector

vector Save_A_Values_A5_B5      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A5              to "k"
   set B5              to "x"
end vector

vector Save_B_Values_A5_B5      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A5              to "x"
   set B5              to "k"
end vector

vector Clk_A_high_A5_B5            !Clock A and latch values when storing data.
   initialize to Save_Values_A5_B5
   set Clk_A   to "1"
end vector

vector Clk_A_low_A5_B5
   initialize to Save_Values_A5_B5
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A5_B5         !Clock A and latch values
   initialize to Save_A_Values_A5_B5  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A5_B5
   initialize to Save_A_Values_A5_B5
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A5_B5       !Clock A and latch values
   initialize to Save_B_Values_A5_B5  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A5_B5
   initialize to Save_B_Values_A5_B5
   set Clk_A   to "0"
end vector

vector Clk_B_high_A5_B5               !Latch values when storing data.
   initialize to Save_Values_A5_B5
   set Clk_B   to "1"
end vector

vector Clk_B_low_A5_B5
   initialize to Save_Values_A5_B5
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A5_B5          !Clock B and latch values when
   initialize to Save_B_Values_A5_B5  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A5_B5
   initialize to Save_B_Values_A5_B5
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A5_B5       !Clock B and latch values
   initialize to Save_A_Values_A5_B5  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A5_B5
   initialize to Save_A_Values_A5_B5
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A5_B5             !Enable clock A when in the storage mode.
   initialize to Save_Values_A5_B5
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A5_B5       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A5_B5
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A5_B5      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A5_B5
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A5_B5     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A5_B5
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A5_B5    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A5_B5
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A5_B5             !Enable clock B when in storage mode.
   initialize to Save_Values_A5_B5
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A5_B5       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A5_B5
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A5_B5      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A5_B5
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A5_B5     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A5_B5
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A5_B5    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A5_B5
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A5_B5       !Enable A to B output.
   initialize to Save_A_Values_A5_B5
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A5_B5     !Enable output received by A from B.
   initialize to Save_B_Values_A5_B5
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A5_B5       !Enable B to A output.
   initialize to Save_B_Values_A5_B5
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A5_B5     !Enable output received by B from A.
   initialize to Save_A_Values_A5_B5
   set OutputB_to_A to "1"
end vector


vector A5_to_B5_0
   initialize to Save_A_Values_A5_B5
   drive A5
   set A5     to "0"
end vector

vector A5_to_B5_1
   initialize to Save_A_Values_A5_B5
   drive A5
   set A5     to "1"
end vector

vector B5_to_A5_0
   initialize to Save_B_Values_A5_B5
   drive B5
   set B5     to "0"
end vector

vector B5_to_A5_1
   initialize to Save_B_Values_A5_B5
   drive B5
   set B5     to "1"
end vector

vector Output_B5_0
   initialize to Save_A_Values_A5_B5
   receive B5
   set B5     to "0"
end vector

vector Output_B5_1
   initialize to Save_A_Values_A5_B5
   receive B5
   set B5     to "1"
end vector

vector Output_A5_0
   initialize to Save_B_Values_A5_B5
   receive A5
   set A5     to "0"
end vector

vector Output_A5_1
   initialize to Save_B_Values_A5_B5
   receive A5
   set A5     to "1"
end vector

vector Set_Values_A6_B6         !Set the device with known values.
   drive A6
   drive B6
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A6              to "0"
   set B6              to "0"
end vector

vector Save_Values_A6_B6        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A6              to "k"
   set B6              to "k"
end vector

vector Save_A_Values_A6_B6      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A6              to "k"
   set B6              to "x"
end vector

vector Save_B_Values_A6_B6      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A6              to "x"
   set B6              to "k"
end vector

vector Clk_A_high_A6_B6            !Clock A and latch values when storing data.
   initialize to Save_Values_A6_B6
   set Clk_A   to "1"
end vector

vector Clk_A_low_A6_B6
   initialize to Save_Values_A6_B6
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A6_B6         !Clock A and latch values
   initialize to Save_A_Values_A6_B6  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A6_B6
   initialize to Save_A_Values_A6_B6
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A6_B6       !Clock A and latch values
   initialize to Save_B_Values_A6_B6  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A6_B6
   initialize to Save_B_Values_A6_B6
   set Clk_A   to "0"
end vector

vector Clk_B_high_A6_B6               !Latch values when storing data.
   initialize to Save_Values_A6_B6
   set Clk_B   to "1"
end vector

vector Clk_B_low_A6_B6
   initialize to Save_Values_A6_B6
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A6_B6          !Clock B and latch values when
   initialize to Save_B_Values_A6_B6  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A6_B6
   initialize to Save_B_Values_A6_B6
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A6_B6       !Clock B and latch values
   initialize to Save_A_Values_A6_B6  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A6_B6
   initialize to Save_A_Values_A6_B6
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A6_B6             !Enable clock A when in the storage mode.
   initialize to Save_Values_A6_B6
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A6_B6       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A6_B6
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A6_B6      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A6_B6
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A6_B6     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A6_B6
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A6_B6    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A6_B6
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A6_B6             !Enable clock B when in storage mode.
   initialize to Save_Values_A6_B6
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A6_B6       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A6_B6
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A6_B6      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A6_B6
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A6_B6     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A6_B6
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A6_B6    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A6_B6
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A6_B6       !Enable A to B output.
   initialize to Save_A_Values_A6_B6
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A6_B6     !Enable output received by A from B.
   initialize to Save_B_Values_A6_B6
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A6_B6       !Enable B to A output.
   initialize to Save_B_Values_A6_B6
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A6_B6     !Enable output received by B from A.
   initialize to Save_A_Values_A6_B6
   set OutputB_to_A to "1"
end vector


vector A6_to_B6_0
   initialize to Save_A_Values_A6_B6
   drive A6
   set A6     to "0"
end vector

vector A6_to_B6_1
   initialize to Save_A_Values_A6_B6
   drive A6
   set A6     to "1"
end vector

vector B6_to_A6_0
   initialize to Save_B_Values_A6_B6
   drive B6
   set B6     to "0"
end vector

vector B6_to_A6_1
   initialize to Save_B_Values_A6_B6
   drive B6
   set B6     to "1"
end vector

vector Output_B6_0
   initialize to Save_A_Values_A6_B6
   receive B6
   set B6     to "0"
end vector

vector Output_B6_1
   initialize to Save_A_Values_A6_B6
   receive B6
   set B6     to "1"
end vector

vector Output_A6_0
   initialize to Save_B_Values_A6_B6
   receive A6
   set A6     to "0"
end vector

vector Output_A6_1
   initialize to Save_B_Values_A6_B6
   receive A6
   set A6     to "1"
end vector

vector Set_Values_A7_B7         !Set the device with known values.
   drive A7
   drive B7
   set OutputA_to_B    to "1"
   set OutputB_to_A    to "1"
   set Clk_A           to "0"
   set Clk_B           to "0"
   set Clk_Enable_A    to "0"
   set Clk_Enable_B    to "0"
   set A7              to "0"
   set B7              to "0"
end vector

vector Save_Values_A7_B7        !Keep values in known state.
   drive Side_A
   drive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set A7              to "k"
   set B7              to "k"
end vector

vector Save_A_Values_A7_B7      !Save values when driving A and receiving at B.
   drive Side_A
   receive Side_B
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A7              to "k"
   set B7              to "x"
end vector

vector Save_B_Values_A7_B7      !Save values when driving B and receiving at A.
   drive Side_B
   receive Side_A
   set OutputA_to_B    to "k"
   set OutputB_to_A    to "k"
   set Clk_A           to "k"
   set Clk_B           to "k"
   set Clk_Enable_A    to "k"
   set Clk_Enable_B    to "k"
   set A7              to "x"
   set B7              to "k"
end vector

vector Clk_A_high_A7_B7            !Clock A and latch values when storing data.
   initialize to Save_Values_A7_B7
   set Clk_A   to "1"
end vector

vector Clk_A_low_A7_B7
   initialize to Save_Values_A7_B7
   set Clk_A   to "0"
end vector

vector Clk_A_drive_high_A7_B7         !Clock A and latch values
   initialize to Save_A_Values_A7_B7  !when driving A and receiving B.
   set Clk_A   to "1"
end vector

vector Clk_A_drive_low_A7_B7
   initialize to Save_A_Values_A7_B7
   set Clk_A   to "0"
end vector

vector Clk_A_receive_high_A7_B7       !Clock A and latch values
   initialize to Save_B_Values_A7_B7  !when Side A is receiving.
   set Clk_A   to "1"
end vector

vector Clk_A_receive_low_A7_B7
   initialize to Save_B_Values_A7_B7
   set Clk_A   to "0"
end vector

vector Clk_B_high_A7_B7               !Latch values when storing data.
   initialize to Save_Values_A7_B7
   set Clk_B   to "1"
end vector

vector Clk_B_low_A7_B7
   initialize to Save_Values_A7_B7
   set Clk_B   to "0"
end vector

vector Clk_B_drive_low_A7_B7          !Clock B and latch values when
   initialize to Save_B_Values_A7_B7  !driving B and receiving A.
   set Clk_B   to "0"
end vector

vector Clk_B_drive_high_A7_B7
   initialize to Save_B_Values_A7_B7
   set Clk_B   to "1"
end vector

vector Clk_B_receive_high_A7_B7       !Clock B and latch values
   initialize to Save_A_Values_A7_B7  !when Side B is receiving.
   set Clk_B   to "1"
end vector

vector Clk_B_receive_low_A7_B7
   initialize to Save_A_Values_A7_B7
   set Clk_B    to "0"
end vector

vector Clk_A_Enable_A7_B7             !Enable clock A when in the storage mode.
   initialize to Save_Values_A7_B7
   set Clk_Enable_A  to "0"
end vector

vector Clk_enable_A_drive_A7_B7       !Enable clock A when transmitting A to B.
   initialize to Save_A_Values_A7_B7
   set Clk_Enable_A  to "0"
end vector

vector Clk_disable_A_drive_A7_B7      !Disable clock A when transmitting A to B.
   initialize to Save_A_Values_A7_B7
   set Clk_Enable_A  to "1"
end vector

vector Clk_enable_A_receive_A7_B7     !Enable clock A when receiving at A.
   initialize to Save_B_Values_A7_B7
   set Clk_enable_A  to "0"
end vector

vector Clk_disable_A_receive_A7_B7    !Disable clock A when receiving at A.
   initialize to Save_B_Values_A7_B7
   set Clk_Enable_A  to "1"
end vector

vector Clk_B_enable_A7_B7             !Enable clock B when in storage mode.
   initialize to Save_Values_A7_B7
   set Clk_Enable_B  to "0"
end vector

vector Clk_enable_B_drive_A7_B7       !Enable clock B when transmitting B to A
   initialize to Save_B_Values_A7_B7
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_drive_A7_B7      !Disable clock B when transmitting B to A.
   initialize to Save_B_Values_A7_B7
   set Clk_Enable_B  to "1"
end vector

vector Clk_enable_B_receive_A7_B7     !Enable clock B when transmitting A to B.
   initialize to Save_A_Values_A7_B7
   set Clk_Enable_B  to "0"
end vector

vector Clk_disable_B_receive_A7_B7    !Disable clock B when transmitting A to B.
   initialize to Save_A_Values_A7_B7
   set Clk_Enable_B  to "1"
end vector

vector OutputA_to_B_Drive_A7_B7       !Enable A to B output.
   initialize to Save_A_Values_A7_B7
   set OutputA_to_B to "0"
end vector

vector OutputA_to_B_Receive_A7_B7     !Enable output received by A from B.
   initialize to Save_B_Values_A7_B7
   set OutputA_to_B to "1"
end vector

vector OutputB_to_A_Drive_A7_B7       !Enable B to A output.
   initialize to Save_B_Values_A7_B7
   set OutputB_to_A to "0"
end vector

vector OutputB_to_A_Receive_A7_B7     !Enable output received by B from A.
   initialize to Save_A_Values_A7_B7
   set OutputB_to_A to "1"
end vector


vector A7_to_B7_0
   initialize to Save_A_Values_A7_B7
   drive A7
   set A7     to "0"
end vector

vector A7_to_B7_1
   initialize to Save_A_Values_A7_B7
   drive A7
   set A7     to "1"
end vector

vector B7_to_A7_0
   initialize to Save_B_Values_A7_B7
   drive B7
   set B7     to "0"
end vector

vector B7_to_A7_1
   initialize to Save_B_Values_A7_B7
   drive B7
   set B7     to "1"
end vector

vector Output_B7_0
   initialize to Save_A_Values_A7_B7
   receive B7
   set B7     to "0"
end vector

vector Output_B7_1
   initialize to Save_A_Values_A7_B7
   receive B7
   set B7     to "1"
end vector

vector Output_A7_0
   initialize to Save_B_Values_A7_B7
   receive A7
   set A7     to "0"
end vector

vector Output_A7_1
   initialize to Save_B_Values_A7_B7
   receive A7
   set A7     to "1"
end vector

!********************************************************************
!                    SUBROUTINE SECTION BEGINS
!********************************************************************

!This subroutine sets the transceiver into a known state by
!storing zeros from the bidirectional lines (Side A and Side B)
!into its registers.

sub Storage

   execute Set_values           !Set to a known state
   execute Clk_A_enable         !clock to enable
   execute Clk_B_enable         !then save values.
   execute Clk_A_high
   execute Clk_B_high
   execute Save_Values

end sub

!********************************************************************
!                    UNIT SECTION BEGINS
!********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with A0 and B0.

unit   "awaretest A0 to B0 Test"

   execute Set_values_A0_B0           !Set to a known state
   execute Clk_A_enable_A0_B0         !clock to enable
   execute Clk_B_enable_A0_B0         !then save values.
   execute Clk_A_high_A0_B0
   execute Clk_B_high_A0_B0
   execute Save_Values_A0_B0

   execute Clk_A_drive_low_A0_B0
   execute OutputA_to_B_Drive_A0_B0
   execute OutputB_to_A_Receive_A0_B0
   execute Clk_Enable_A_Drive_A0_B0
   execute A0_to_B0_0
   execute Clk_A_Drive_High_A0_B0
   execute Save_A_Values_A0_B0

   execute Clk_Enable_B_Receive_A0_B0
   execute Output_B0_0
   execute Clk_B_receive_high_A0_B0

   execute Set_values_A0_B0           !Set to a known state
   execute Clk_A_enable_A0_B0         !clock to enable
   execute Clk_B_enable_A0_B0         !then save values.
   execute Clk_A_high_A0_B0
   execute Clk_B_high_A0_B0
   execute Save_Values_A0_B0

   execute Clk_A_drive_low_A0_B0
   execute OutputA_to_B_Drive_A0_B0
   execute OutputB_to_A_Receive_A0_B0
   execute Clk_Enable_A_Drive_A0_B0
   execute A0_to_B0_1
   execute Clk_A_Drive_High_A0_B0
   execute Save_A_Values_A0_B0

   execute Clk_Enable_B_Receive_A0_B0
   execute Output_B0_1
   execute Clk_B_receive_high_A0_B0

end unit

unit   "awaretest A1 to B1 Test"

   execute Set_values_A1_B1           !Set to a known state
   execute Clk_A_enable_A1_B1         !clock to enable
   execute Clk_B_enable_A1_B1         !then save values.
   execute Clk_A_high_A1_B1
   execute Clk_B_high_A1_B1
   execute Save_Values_A1_B1

   execute Clk_A_drive_low_A1_B1
   execute OutputA_to_B_Drive_A1_B1
   execute OutputB_to_A_Receive_A1_B1
   execute Clk_Enable_A_Drive_A1_B1
   execute A1_to_B1_0
   execute Clk_A_Drive_High_A1_B1
   execute Save_A_Values_A1_B1

   execute Clk_Enable_B_Receive_A1_B1
   execute Output_B1_0
   execute Clk_B_receive_high_A1_B1

   execute Set_values_A1_B1           !Set to a known state
   execute Clk_A_enable_A1_B1         !clock to enable
   execute Clk_B_enable_A1_B1         !then save values.
   execute Clk_A_high_A1_B1
   execute Clk_B_high_A1_B1
   execute Save_Values_A1_B1

   execute Clk_A_drive_low_A1_B1
   execute OutputA_to_B_Drive_A1_B1
   execute OutputB_to_A_Receive_A1_B1
   execute Clk_Enable_A_Drive_A1_B1
   execute A1_to_B1_1
   execute Clk_A_Drive_High_A1_B1
   execute Save_A_Values_A1_B1

   execute Clk_Enable_B_Receive_A1_B1
   execute Output_B1_1
   execute Clk_B_receive_high_A1_B1

end unit

unit   "awaretest A2 to B2 Test"

   execute Set_values_A2_B2           !Set to a known state
   execute Clk_A_enable_A2_B2         !clock to enable
   execute Clk_B_enable_A2_B2         !then save values.
   execute Clk_A_high_A2_B2
   execute Clk_B_high_A2_B2
   execute Save_Values_A2_B2

   execute Clk_A_drive_low_A2_B2
   execute OutputA_to_B_Drive_A2_B2
   execute OutputB_to_A_Receive_A2_B2
   execute Clk_Enable_A_Drive_A2_B2
   execute A2_to_B2_0
   execute Clk_A_Drive_High_A2_B2
   execute Save_A_Values_A2_B2

   execute Clk_Enable_B_Receive_A2_B2
   execute Output_B2_0
   execute Clk_B_receive_high_A2_B2

   execute Set_values_A2_B2           !Set to a known state
   execute Clk_A_enable_A2_B2         !clock to enable
   execute Clk_B_enable_A2_B2         !then save values.
   execute Clk_A_high_A2_B2
   execute Clk_B_high_A2_B2
   execute Save_Values_A2_B2

   execute Clk_A_drive_low_A2_B2
   execute OutputA_to_B_Drive_A2_B2
   execute OutputB_to_A_Receive_A2_B2
   execute Clk_Enable_A_Drive_A2_B2
   execute A2_to_B2_1
   execute Clk_A_Drive_High_A2_B2
   execute Save_A_Values_A2_B2

   execute Clk_Enable_B_Receive_A2_B2
   execute Output_B2_1
   execute Clk_B_receive_high_A2_B2

end unit

unit   "awaretest A3 to B3 Test"

   execute Set_values_A3_B3           !Set to a known state
   execute Clk_A_enable_A3_B3         !clock to enable
   execute Clk_B_enable_A3_B3         !then save values.
   execute Clk_A_high_A3_B3
   execute Clk_B_high_A3_B3
   execute Save_Values_A3_B3

   execute Clk_A_drive_low_A3_B3
   execute OutputA_to_B_Drive_A3_B3
   execute OutputB_to_A_Receive_A3_B3
   execute Clk_Enable_A_Drive_A3_B3
   execute A3_to_B3_0
   execute Clk_A_Drive_High_A3_B3
   execute Save_A_Values_A3_B3

   execute Clk_Enable_B_Receive_A3_B3
   execute Output_B3_0
   execute Clk_B_receive_high_A3_B3

   execute Set_values_A3_B3           !Set to a known state
   execute Clk_A_enable_A3_B3         !clock to enable
   execute Clk_B_enable_A3_B3         !then save values.
   execute Clk_A_high_A3_B3
   execute Clk_B_high_A3_B3
   execute Save_Values_A3_B3

   execute Clk_A_drive_low_A3_B3
   execute OutputA_to_B_Drive_A3_B3
   execute OutputB_to_A_Receive_A3_B3
   execute Clk_Enable_A_Drive_A3_B3
   execute A3_to_B3_1
   execute Clk_A_Drive_High_A3_B3
   execute Save_A_Values_A3_B3

   execute Clk_Enable_B_Receive_A3_B3
   execute Output_B3_1
   execute Clk_B_receive_high_A3_B3

end unit

unit   "awaretest A4 to B4 Test"

   execute Set_values_A4_B4           !Set to a known state
   execute Clk_A_enable_A4_B4         !clock to enable
   execute Clk_B_enable_A4_B4         !then save values.
   execute Clk_A_high_A4_B4
   execute Clk_B_high_A4_B4
   execute Save_Values_A4_B4

   execute Clk_A_drive_low_A4_B4
   execute OutputA_to_B_Drive_A4_B4
   execute OutputB_to_A_Receive_A4_B4
   execute Clk_Enable_A_Drive_A4_B4
   execute A4_to_B4_0
   execute Clk_A_Drive_High_A4_B4
   execute Save_A_Values_A4_B4

   execute Clk_Enable_B_Receive_A4_B4
   execute Output_B4_0
   execute Clk_B_receive_high_A4_B4

   execute Set_values_A4_B4           !Set to a known state
   execute Clk_A_enable_A4_B4         !clock to enable
   execute Clk_B_enable_A4_B4         !then save values.
   execute Clk_A_high_A4_B4
   execute Clk_B_high_A4_B4
   execute Save_Values_A4_B4

   execute Clk_A_drive_low_A4_B4
   execute OutputA_to_B_Drive_A4_B4
   execute OutputB_to_A_Receive_A4_B4
   execute Clk_Enable_A_Drive_A4_B4
   execute A4_to_B4_1
   execute Clk_A_Drive_High_A4_B4
   execute Save_A_Values_A4_B4

   execute Clk_Enable_B_Receive_A4_B4
   execute Output_B4_1
   execute Clk_B_receive_high_A4_B4

end unit

unit   "awaretest A5 to B5 Test"

   execute Set_values_A5_B5           !Set to a known state
   execute Clk_A_enable_A5_B5         !clock to enable
   execute Clk_B_enable_A5_B5         !then save values.
   execute Clk_A_high_A5_B5
   execute Clk_B_high_A5_B5
   execute Save_Values_A5_B5

   execute Clk_A_drive_low_A5_B5
   execute OutputA_to_B_Drive_A5_B5
   execute OutputB_to_A_Receive_A5_B5
   execute Clk_Enable_A_Drive_A5_B5
   execute A5_to_B5_0
   execute Clk_A_Drive_High_A5_B5
   execute Save_A_Values_A5_B5

   execute Clk_Enable_B_Receive_A5_B5
   execute Output_B5_0
   execute Clk_B_receive_high_A5_B5

   execute Set_values_A5_B5           !Set to a known state
   execute Clk_A_enable_A5_B5         !clock to enable
   execute Clk_B_enable_A5_B5         !then save values.
   execute Clk_A_high_A5_B5
   execute Clk_B_high_A5_B5
   execute Save_Values_A5_B5

   execute Clk_A_drive_low_A5_B5
   execute OutputA_to_B_Drive_A5_B5
   execute OutputB_to_A_Receive_A5_B5
   execute Clk_Enable_A_Drive_A5_B5
   execute A5_to_B5_1
   execute Clk_A_Drive_High_A5_B5
   execute Save_A_Values_A5_B5

   execute Clk_Enable_B_Receive_A5_B5
   execute Output_B5_1
   execute Clk_B_receive_high_A5_B5

end unit

unit   "awaretest A6 to B6 Test"

   execute Set_values_A6_B6           !Set to a known state
   execute Clk_A_enable_A6_B6         !clock to enable
   execute Clk_B_enable_A6_B6         !then save values.
   execute Clk_A_high_A6_B6
   execute Clk_B_high_A6_B6
   execute Save_Values_A6_B6

   execute Clk_A_drive_low_A6_B6
   execute OutputA_to_B_Drive_A6_B6
   execute OutputB_to_A_Receive_A6_B6
   execute Clk_Enable_A_Drive_A6_B6
   execute A6_to_B6_0
   execute Clk_A_Drive_High_A6_B6
   execute Save_A_Values_A6_B6

   execute Clk_Enable_B_Receive_A6_B6
   execute Output_B6_0
   execute Clk_B_receive_high_A6_B6

   execute Set_values_A6_B6           !Set to a known state
   execute Clk_A_enable_A6_B6         !clock to enable
   execute Clk_B_enable_A6_B6         !then save values.
   execute Clk_A_high_A6_B6
   execute Clk_B_high_A6_B6
   execute Save_Values_A6_B6

   execute Clk_A_drive_low_A6_B6
   execute OutputA_to_B_Drive_A6_B6
   execute OutputB_to_A_Receive_A6_B6
   execute Clk_Enable_A_Drive_A6_B6
   execute A6_to_B6_1
   execute Clk_A_Drive_High_A6_B6
   execute Save_A_Values_A6_B6

   execute Clk_Enable_B_Receive_A6_B6
   execute Output_B6_1
   execute Clk_B_receive_high_A6_B6

end unit

unit   "awaretest A7 to B7 Test"

   execute Set_values_A7_B7           !Set to a known state
   execute Clk_A_enable_A7_B7         !clock to enable
   execute Clk_B_enable_A7_B7         !then save values.
   execute Clk_A_high_A7_B7
   execute Clk_B_high_A7_B7
   execute Save_Values_A7_B7

   execute Clk_A_drive_low_A7_B7
   execute OutputA_to_B_Drive_A7_B7
   execute OutputB_to_A_Receive_A7_B7
   execute Clk_Enable_A_Drive_A7_B7
   execute A7_to_B7_0
   execute Clk_A_Drive_High_A7_B7
   execute Save_A_Values_A7_B7

   execute Clk_Enable_B_Receive_A7_B7
   execute Output_B7_0
   execute Clk_B_receive_high_A7_B7

   execute Set_values_A7_B7           !Set to a known state
   execute Clk_A_enable_A7_B7         !clock to enable
   execute Clk_B_enable_A7_B7         !then save values.
   execute Clk_A_high_A7_B7
   execute Clk_B_high_A7_B7
   execute Save_Values_A7_B7

   execute Clk_A_drive_low_A7_B7
   execute OutputA_to_B_Drive_A7_B7
   execute OutputB_to_A_Receive_A7_B7
   execute Clk_Enable_A_Drive_A7_B7
   execute A7_to_B7_1
   execute Clk_A_Drive_High_A7_B7
   execute Save_A_Values_A7_B7

   execute Clk_Enable_B_Receive_A7_B7
   execute Output_B7_1
   execute Clk_B_receive_high_A7_B7

end unit

unit   "awaretest B0 to A0 Test"

   execute Set_values_A0_B0           !Set to a known state
   execute Clk_A_enable_A0_B0         !clock to enable
   execute Clk_B_enable_A0_B0         !then save values.
   execute Clk_A_high_A0_B0
   execute Clk_B_high_A0_B0
   execute Save_Values_A0_B0

   execute Clk_B_drive_low_A0_B0
   execute OutputB_to_A_Drive_A0_B0
   execute OutputA_to_B_Receive_A0_B0
   execute Clk_Enable_B_Drive_A0_B0
   execute B0_to_A0_0
   execute Clk_B_Drive_High_A0_B0
   execute Save_B_Values_A0_B0

   execute Clk_enable_A_receive_A0_B0
   execute Output_A0_0
   execute Clk_A_receive_high_A0_B0

   execute Set_values_A0_B0           !Set to a known state
   execute Clk_A_enable_A0_B0         !clock to enable
   execute Clk_B_enable_A0_B0         !then save values.
   execute Clk_A_high_A0_B0
   execute Clk_B_high_A0_B0
   execute Save_Values_A0_B0

   execute Clk_B_drive_low_A0_B0
   execute OutputB_to_A_Drive_A0_B0
   execute OutputA_to_B_Receive_A0_B0
   execute Clk_Enable_B_Drive_A0_B0
   execute B0_to_A0_1
   execute Clk_B_Drive_High_A0_B0
   execute Save_B_Values_A0_B0

   execute Clk_enable_A_receive_A0_B0
   execute Output_A0_1
   execute Clk_A_receive_high_A0_B0

end unit

unit   "awaretest B1 to A1 Test"

   execute Set_values_A1_B1           !Set to a known state
   execute Clk_A_enable_A1_B1         !clock to enable
   execute Clk_B_enable_A1_B1         !then save values.
   execute Clk_A_high_A1_B1
   execute Clk_B_high_A1_B1
   execute Save_Values_A1_B1

   execute Clk_B_drive_low_A1_B1
   execute OutputB_to_A_Drive_A1_B1
   execute OutputA_to_B_Receive_A1_B1
   execute Clk_Enable_B_Drive_A1_B1
   execute B1_to_A1_0
   execute Clk_B_Drive_High_A1_B1
   execute Save_B_Values_A1_B1

   execute Clk_enable_A_receive_A1_B1
   execute Output_A1_0
   execute Clk_A_receive_high_A1_B1

   execute Set_values_A1_B1           !Set to a known state
   execute Clk_A_enable_A1_B1         !clock to enable
   execute Clk_B_enable_A1_B1         !then save values.
   execute Clk_A_high_A1_B1
   execute Clk_B_high_A1_B1
   execute Save_Values_A1_B1

   execute Clk_B_drive_low_A1_B1
   execute OutputB_to_A_Drive_A1_B1
   execute OutputA_to_B_Receive_A1_B1
   execute Clk_Enable_B_Drive_A1_B1
   execute B1_to_A1_1
   execute Clk_B_Drive_High_A1_B1
   execute Save_B_Values_A1_B1

   execute Clk_enable_A_receive_A1_B1
   execute Output_A1_1
   execute Clk_A_receive_high_A1_B1

end unit

unit   "awaretest B2 to A2 Test"

   execute Set_values_A2_B2           !Set to a known state
   execute Clk_A_enable_A2_B2         !clock to enable
   execute Clk_B_enable_A2_B2         !then save values.
   execute Clk_A_high_A2_B2
   execute Clk_B_high_A2_B2
   execute Save_Values_A2_B2

   execute Clk_B_drive_low_A2_B2
   execute OutputB_to_A_Drive_A2_B2
   execute OutputA_to_B_Receive_A2_B2
   execute Clk_Enable_B_Drive_A2_B2
   execute B2_to_A2_0
   execute Clk_B_Drive_High_A2_B2
   execute Save_B_Values_A2_B2

   execute Clk_enable_A_receive_A2_B2
   execute Output_A2_0
   execute Clk_A_receive_high_A2_B2

   execute Set_values_A2_B2           !Set to a known state
   execute Clk_A_enable_A2_B2         !clock to enable
   execute Clk_B_enable_A2_B2         !then save values.
   execute Clk_A_high_A2_B2
   execute Clk_B_high_A2_B2
   execute Save_Values_A2_B2

   execute Clk_B_drive_low_A2_B2
   execute OutputB_to_A_Drive_A2_B2
   execute OutputA_to_B_Receive_A2_B2
   execute Clk_Enable_B_Drive_A2_B2
   execute B2_to_A2_1
   execute Clk_B_Drive_High_A2_B2
   execute Save_B_Values_A2_B2

   execute Clk_enable_A_receive_A2_B2
   execute Output_A2_1
   execute Clk_A_receive_high_A2_B2

end unit

unit   "awaretest B3 to A3 Test"

   execute Set_values_A3_B3           !Set to a known state
   execute Clk_A_enable_A3_B3         !clock to enable
   execute Clk_B_enable_A3_B3         !then save values.
   execute Clk_A_high_A3_B3
   execute Clk_B_high_A3_B3
   execute Save_Values_A3_B3

   execute Clk_B_drive_low_A3_B3
   execute OutputB_to_A_Drive_A3_B3
   execute OutputA_to_B_Receive_A3_B3
   execute Clk_Enable_B_Drive_A3_B3
   execute B3_to_A3_0
   execute Clk_B_Drive_High_A3_B3
   execute Save_B_Values_A3_B3

   execute Clk_enable_A_receive_A3_B3
   execute Output_A3_0
   execute Clk_A_receive_high_A3_B3

   execute Set_values_A3_B3           !Set to a known state
   execute Clk_A_enable_A3_B3         !clock to enable
   execute Clk_B_enable_A3_B3         !then save values.
   execute Clk_A_high_A3_B3
   execute Clk_B_high_A3_B3
   execute Save_Values_A3_B3

   execute Clk_B_drive_low_A3_B3
   execute OutputB_to_A_Drive_A3_B3
   execute OutputA_to_B_Receive_A3_B3
   execute Clk_Enable_B_Drive_A3_B3
   execute B3_to_A3_1
   execute Clk_B_Drive_High_A3_B3
   execute Save_B_Values_A3_B3

   execute Clk_enable_A_receive_A3_B3
   execute Output_A3_1
   execute Clk_A_receive_high_A3_B3

end unit

unit   "awaretest B4 to A4 Test"

   execute Set_values_A4_B4           !Set to a known state
   execute Clk_A_enable_A4_B4         !clock to enable
   execute Clk_B_enable_A4_B4         !then save values.
   execute Clk_A_high_A4_B4
   execute Clk_B_high_A4_B4
   execute Save_Values_A4_B4

   execute Clk_B_drive_low_A4_B4
   execute OutputB_to_A_Drive_A4_B4
   execute OutputA_to_B_Receive_A4_B4
   execute Clk_Enable_B_Drive_A4_B4
   execute B4_to_A4_0
   execute Clk_B_Drive_High_A4_B4
   execute Save_B_Values_A4_B4

   execute Clk_enable_A_receive_A4_B4
   execute Output_A4_0
   execute Clk_A_receive_high_A4_B4

   execute Set_values_A4_B4           !Set to a known state
   execute Clk_A_enable_A4_B4         !clock to enable
   execute Clk_B_enable_A4_B4         !then save values.
   execute Clk_A_high_A4_B4
   execute Clk_B_high_A4_B4
   execute Save_Values_A4_B4

   execute Clk_B_drive_low_A4_B4
   execute OutputB_to_A_Drive_A4_B4
   execute OutputA_to_B_Receive_A4_B4
   execute Clk_Enable_B_Drive_A4_B4
   execute B4_to_A4_1
   execute Clk_B_Drive_High_A4_B4
   execute Save_B_Values_A4_B4

   execute Clk_enable_A_receive_A4_B4
   execute Output_A4_1
   execute Clk_A_receive_high_A4_B4

end unit

unit   "awaretest B5 to A5 Test"

   execute Set_values_A5_B5           !Set to a known state
   execute Clk_A_enable_A5_B5         !clock to enable
   execute Clk_B_enable_A5_B5         !then save values.
   execute Clk_A_high_A5_B5
   execute Clk_B_high_A5_B5
   execute Save_Values_A5_B5

   execute Clk_B_drive_low_A5_B5
   execute OutputB_to_A_Drive_A5_B5
   execute OutputA_to_B_Receive_A5_B5
   execute Clk_Enable_B_Drive_A5_B5
   execute B5_to_A5_0
   execute Clk_B_Drive_High_A5_B5
   execute Save_B_Values_A5_B5

   execute Clk_enable_A_receive_A5_B5
   execute Output_A5_0
   execute Clk_A_receive_high_A5_B5

   execute Set_values_A5_B5           !Set to a known state
   execute Clk_A_enable_A5_B5         !clock to enable
   execute Clk_B_enable_A5_B5         !then save values.
   execute Clk_A_high_A5_B5
   execute Clk_B_high_A5_B5
   execute Save_Values_A5_B5

   execute Clk_B_drive_low_A5_B5
   execute OutputB_to_A_Drive_A5_B5
   execute OutputA_to_B_Receive_A5_B5
   execute Clk_Enable_B_Drive_A5_B5
   execute B5_to_A5_1
   execute Clk_B_Drive_High_A5_B5
   execute Save_B_Values_A5_B5

   execute Clk_enable_A_receive_A5_B5
   execute Output_A5_1
   execute Clk_A_receive_high_A5_B5

end unit

unit   "awaretest B6 to A6 Test"

   execute Set_values_A6_B6           !Set to a known state
   execute Clk_A_enable_A6_B6         !clock to enable
   execute Clk_B_enable_A6_B6         !then save values.
   execute Clk_A_high_A6_B6
   execute Clk_B_high_A6_B6
   execute Save_Values_A6_B6

   execute Clk_B_drive_low_A6_B6
   execute OutputB_to_A_Drive_A6_B6
   execute OutputA_to_B_Receive_A6_B6
   execute Clk_Enable_B_Drive_A6_B6
   execute B6_to_A6_0
   execute Clk_B_Drive_High_A6_B6
   execute Save_B_Values_A6_B6

   execute Clk_enable_A_receive_A6_B6
   execute Output_A6_0
   execute Clk_A_receive_high_A6_B6

   execute Set_values_A6_B6           !Set to a known state
   execute Clk_A_enable_A6_B6         !clock to enable
   execute Clk_B_enable_A6_B6         !then save values.
   execute Clk_A_high_A6_B6
   execute Clk_B_high_A6_B6
   execute Save_Values_A6_B6

   execute Clk_B_drive_low_A6_B6
   execute OutputB_to_A_Drive_A6_B6
   execute OutputA_to_B_Receive_A6_B6
   execute Clk_Enable_B_Drive_A6_B6
   execute B6_to_A6_1
   execute Clk_B_Drive_High_A6_B6
   execute Save_B_Values_A6_B6

   execute Clk_enable_A_receive_A6_B6
   execute Output_A6_1
   execute Clk_A_receive_high_A6_B6

end unit

unit   "awaretest B7 to A7 Test"

   execute Set_values_A7_B7           !Set to a known state
   execute Clk_A_enable_A7_B7         !clock to enable
   execute Clk_B_enable_A7_B7         !then save values.
   execute Clk_A_high_A7_B7
   execute Clk_B_high_A7_B7
   execute Save_Values_A7_B7

   execute Clk_B_drive_low_A7_B7
   execute OutputB_to_A_Drive_A7_B7
   execute OutputA_to_B_Receive_A7_B7
   execute Clk_Enable_B_Drive_A7_B7
   execute B7_to_A7_0
   execute Clk_B_Drive_High_A7_B7
   execute Save_B_Values_A7_B7

   execute Clk_enable_A_receive_A7_B7
   execute Output_A7_0
   execute Clk_A_receive_high_A7_B7

   execute Set_values_A7_B7           !Set to a known state
   execute Clk_A_enable_A7_B7         !clock to enable
   execute Clk_B_enable_A7_B7         !then save values.
   execute Clk_A_high_A7_B7
   execute Clk_B_high_A7_B7
   execute Save_Values_A7_B7

   execute Clk_B_drive_low_A7_B7
   execute OutputB_to_A_Drive_A7_B7
   execute OutputA_to_B_Receive_A7_B7
   execute Clk_Enable_B_Drive_A7_B7
   execute B7_to_A7_1
   execute Clk_B_Drive_High_A7_B7
   execute Save_B_Values_A7_B7

   execute Clk_enable_A_receive_A7_B7
   execute Output_A7_1
   execute Clk_A_receive_high_A7_B7

end unit

unit "A-to-B Operation"

!The first unit puts the transceiver into A to B operation
!by driving side A and receiving at side B.  First the hex
!number 55 is used as data and then AA is used.

   call Storage                 !Set into known state.

   execute Clk_A_drive_low
   execute OutputA_to_B_Drive
   execute OutputB_to_A_Receive
   execute Clk_Enable_A_Drive
   execute A_to_B_55            !Place 55h on input lines.
   execute Clk_A_Drive_High
   execute Save_A_Values

   execute Clk_Enable_B_Receive
   execute Output_B_55          !Check output.
   execute Clk_B_receive_high

   call Storage                 !Set into known state.

   execute Clk_A_drive_low
   execute OutputA_to_B_drive
   execute OutputB_to_A_receive
   execute Clk_Enable_A_drive
   execute A_to_B_AA            !Place AAh on the input lines.
   execute Clk_A_drive_high
   execute Save_A_values

   execute Clk_Enable_B_Receive
   execute Output_B_AA          !Check output.
   execute Clk_B_receive_high

end unit

unit "B-to-A Operation"

!The second unit puts the transceiver into B to A operation using
!the same method and the same data as in the previous unit.

   call Storage                 !Set up device into known state.

   execute Clk_B_drive_low
   execute OutputB_to_A_Drive
   execute OutputA_to_B_Receive
   execute Clk_Enable_B_Drive
   execute B_to_A_55            !Place 55h on input lines.
   execute Clk_B_Drive_High
   execute Save_B_Values

   execute Clk_enable_A_receive
   execute Output_A_55          !Check output.
   execute Clk_A_receive_high

   call Storage                 !Set device into known state.

   execute Clk_B_drive_low
   execute OutputB_to_A_Drive
   execute OutputA_to_B_Receive
   execute Clk_Enable_B_Drive
   execute B_to_A_AA            !Place AAh on input lines.
   execute Clk_B_Drive_High
   execute Save_B_Values

   execute Clk_enable_A_receive
   execute Output_A_AA          !Check output.
   execute Clk_A_receive_high

end unit


unit "Test Clock enable pins"

!This unit can be commented out if the Clock enable pins are
!not going to be tested.

   call Storage                 !Test Clk_Enable_A.

   execute Clk_A_drive_low
   execute OutputA_to_B_Drive
   execute OutputB_to_A_Receive
   execute Clk_Enable_A_Drive
   execute A_to_B_55            !Place 55h on input lines.
   execute Clk_A_Drive_High
   execute Save_A_Values

   call Storage                 !Set into a known state.

   execute Clk_disable_A_Drive  !Disable Clock A enable pin.
   execute Clk_A_drive_low
   execute Clk_disable_B_receive
   execute OutputA_to_B_Drive
   execute OutputB_to_A_Receive
   execute A_to_B_AA            !Place AAh on input lines.
   execute Clk_A_Drive_High
   execute Save_A_Values

   execute Clk_enable_B_receive
   execute Output_B_55          !Check output.
   execute Clk_B_receive_high


   call Storage                 !Test Clock_enable_B pin.

   execute Clk_B_drive_low
   execute OutputB_to_A_Drive
   execute OutputA_to_B_Receive
   execute Clk_Enable_B_Drive
   execute B_to_A_55            !Place 55h on input lines.
   execute Clk_B_Drive_High
   execute Save_B_Values

   call Storage                 !Set up in a known state.

   execute Clk_B_drive_low
   execute OutputB_to_A_Drive
   execute OutputA_to_B_Receive
   execute Clk_disable_B_Drive  !Disable Clock B enable pin.
   execute B_to_A_00
   execute Clk_B_Drive_High
   execute Save_B_Values


   execute Clk_disable_B_drive
   execute Clk_enable_A_receive
   execute Output_A_55          !Check output.
   execute Clk_A_receive_high


end unit