!!!!    6    0    1  989956177  Vfb55                                         

! Device           : 8755
! Function         : 16,384-Bit EPROM with I_O
! revision         : B.01.00
! safeguard        : med_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 400n
receive delay 300n

assign    VCC            to pins   40
assign    VDD            to pins   5
assign    GND            to pins   20

assign    Addr_bus       to pins   23,22,21,19,18,17,16,15
assign    Addr_bus       to pins   14,13,12
assign    Data_bus       to pins   19,18,17,16,15,14,13,12

assign    Port_select    to pins   13,12

assign    ALE            to pins   11

assign    Chip_enable    to pins   2
assign    Chip_enable_bar to pins  1

assign    IO_M_bar       to pins   7
assign    Read_bar       to pins   9
assign    IO_Read_bar    to pins   8
assign    IO_Write_bar   to pins   10

assign    Clock          to pins   3

assign    Ready          to pins   6

assign    Port_A         to pins   31,30,29,28,27,26,25,24
assign    Port_B         to pins   39,38,37,36,35,34,33,32
assign    Ports          to pins   31,30,29,28,27,26,25,24
assign    Ports          to pins   39,38,37
assign    Ports          to pins   36,35,34,33,32

assign    Reset          to pins   4

assign    Disable_pins_1  to pins   1,2,3
assign    Disable_pins_2  to pins   4,3
assign    Disable_pins_3  to pins   7,9,3
assign    Disable_pins_4  to pins   8,3

family    TTL

format    hexadecimal Addr_bus, Data_bus, Port_A, Port_B,Ports

power     VCC, VDD, GND

bidirectional    Port_A, Port_B, Ports,Data_bus,Addr_bus,Port_select

inputs    ALE,  Clock, Reset
inputs    IO_M_bar, IO_Write_bar, IO_Read_bar, Read_bar
inputs    Chip_enable, Chip_enable_bar

outputs   Ready

when     Chip_enable       is "0"   inactive    Data_bus
when     Chip_enable_bar   is "1"   inactive    Data_bus
when     IO_Write_bar      is "0"   inputs      Data_bus
when     IO_Read_bar       is "0"   outputs     Data_bus

trace    Data_bus  to  ALE,  Clock, Reset,Read_bar,Port_A,Port_B
trace    Data_bus  to  IO_M_bar, IO_Write_bar, IO_Read_bar
trace    Data_bus  to  Chip_enable, Chip_enable_bar,Addr_bus

trace    Addr_bus  to  ALE,  Clock, Reset,Read_bar,Data_bus
trace    Addr_bus  to  IO_M_bar, IO_Write_bar, IO_Read_bar
trace    Addr_bus  to  Chip_enable, Chip_enable_bar,Addr_bus

trace    Ready     to  ALE,  Clock, Reset,Read_bar
trace    Ready     to  IO_M_bar, IO_Write_bar, IO_Read_bar
trace    Ready     to  Chip_enable, Chip_enable_bar

trace    Port_A    to  ALE,  Clock, Reset,Read_bar,Data_bus
trace    Port_A    to  IO_M_bar, IO_Write_bar, IO_Read_bar
trace    Port_A    to  Chip_enable, Chip_enable_bar,Addr_bus

trace    Port_B    to  ALE,  Clock, Reset,Read_bar,Data_bus
trace    Port_B    to  IO_M_bar, IO_Write_bar, IO_Read_bar
trace    Port_B    to  Chip_enable, Chip_enable_bar,Addr_bus

disable   Data_bus       with  Disable_pins_1    to   "10T"  10 times
disable   Addr_bus       with  Disable_pins_1    to   "10T"  10 times
disable   Ready          with  Disable_pins_1    to   "10T"  10 times
disable   Ports          with  Disable_pins_1    to   "10T"  10 times
disable   Ports          with  Disable_pins_2    to   "1T"   10 times
disable   Ports          with  Disable_pins_3    to   "10T"  10 times
disable   Ports          with  Disable_pins_4    to   "0T"  10 times

!***************************************************************
!***************************************************************
!***************************************************************
vector    Normal_operation
   set    Chip_enable             to "1"
   set    Chip_enable_bar         to "0"
   set    ALE                     to "0"
   set    IO_M_bar                to "0"
   set    Read_bar                to "1"
   set    IO_Read_bar             to "1"
   set    IO_Write_bar            to "1"
   set    Clock                   to "1"
   set    Reset                   to "0"
end vector

vector    Keep_on_Control_lines
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    Read_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
end vector

vector    Keep_on_AD1_2_lines
   drive  Port_select
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    Read_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
   set    Port_select             to "KK"
end vector

vector    Keep_on_Data_lines
   drive  Data_bus
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    Read_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
   set    Data_bus                to "KK"
end vector

vector    Keep_on_Addr_lines
   drive  Addr_bus
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    Read_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
   set    Addr_bus                to "KKK"
end vector


vector    Keep_on_Port_A
   drive  Port_A
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    Read_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
   set    Port_A                  to  "KK"
end vector

vector    Keep_on_Port_B
   drive  Port_B
   set    Chip_enable             to "K"
   set    Chip_enable_bar         to "K"
   set    ALE                     to "K"
   set    IO_M_bar                to "K"
   set    ReAd_bar                to "K"
   set    IO_Read_bar             to "K"
   set    IO_Write_bar            to "K"
   set    Clock                   to "K"
   set    Reset                   to "K"
   set    Port_B                  to  "KK"
end vector


vector    Clock_low
   initialize to Keep_on_control_lines
   set    Clock                   to "0"
end vector

vector    Clock_high
   initialize to Keep_on_control_lines
   set    Clock                   to "1"
end vector

vector    Clock_low_Keep_on_Data_lines
   initialize to Keep_on_Data_lines
   set    Clock                   to "0"
end vector

vector    Clock_high_Keep_on_Data_lines
   initialize to Keep_on_Data_lines
   set    Clock                   to "1"
end vector

vector    Clock_low_Keep_on_Addr_lines
   initialize to Keep_on_Addr_lines
   set    Clock                   to "0"
end vector

vector    Clock_high_Keep_on_Addr_lines
   initialize to Keep_on_Addr_lines
   set    Clock                   to "1"
end vector


vector    Clock_low_keep_on_AD1_2_lines
   initialize to Keep_on_AD1_2_lines
   set    Clock                   to "0"
end vector

vector    Clock_high_Keep_on_AD1_2_lines
   initialize to Keep_on_AD1_2_lines
   set    Clock                   to "1"
end vector


vector    Clock_low_Keep_on_Port_A
   initialize to Keep_on_Port_A
   set    Clock                   to "0"
end vector

vector    Clock_high_Keep_on_Port_A
   initialize to Keep_on_Port_A
   set    Clock                   to "1"
end vector

vector    Clock_low_Keep_on_Port_B
   initialize to Keep_on_Port_B
   set    Clock                   to "0"
end vector

vector    Clock_high_Keep_on_Port_B
   initialize to Keep_on_Port_B
   set    Clock                   to "1"
end vector


vector  Reset_low
   initialize to Keep_on_control_lines
   set    Reset                   to "0"
end vector

vector  Reset_high
   initialize to Keep_on_control_lines
   set    Reset                   to "1"
end vector


vector    Chip_enable_low
   initialize to Keep_on_control_lines
   set    Chip_enable             to "0"
end vector

vector    Chip_enable_high
   initialize to Keep_on_control_lines
   set    Chip_enable             to "1"
end vector

vector    Chip_enable_bar_low
   initialize to Keep_on_control_lines
   set    Chip_enable_bar          to "0"
end vector

vector    Chip_enable_bar_high
   initialize to Keep_on_control_lines
   set    Chip_enable_bar         to "1"
end vector


vector    Ready_low
   initialize to Keep_on_control_lines
   set    Ready                   to "0"
end vector

vector    Ready_high
   initialize to Keep_on_control_lines
   set    Ready                   to "1"
end vector

vector    ALE_low_Keep_on_Addr_lines
   initialize to Keep_on_Addr_lines
   set    ALE                     to "0"
end vector

vector    ALE_low
   initialize to Keep_on_Control_lines
   set    ALE                     to "0"
end vector


vector    ALE_low_keep_AD1_2_lines
   initialize to Keep_on_AD1_2_lines
   set    ALE                     to "0"
end vector

vector    ALE_high
   initialize to Keep_on_control_lines
   set    ALE                     to "1"
end vector

vector    Port_A_select
   initialize to Keep_on_control_lines
   drive  Port_select
   set    Port_select             to "00"
end vector


vector   Port_B_select
   initialize to Keep_on_control_lines
   drive  Port_select
   set    Port_select             to "01"
end vector

vector    Port_A_DDR_select
   initialize to Keep_on_control_lines
   drive  Port_select
   set    Port_select             to "10"
end vector

vector    Port_B_DDR_select
   initialize to Keep_on_control_lines
   drive  Port_select
   set    Port_select             to "11"
end vector


vector    IO_M_bar_low
   initialize to Keep_on_Control_lines
   set    IO_M_bar                to "0"
end vector

vector    IO_M_bar_high
   initialize to Keep_on_Control_lines
   set    IO_M_bar                to "1"
end vector


vector    IO_M_bar_low_Keep_on_Port_A
   initialize to Keep_on_Port_A
   set    IO_M_bar                to "0"
end vector


vector    IO_M_bar_high_keep_on_Port_A
   initialize to Keep_on_Port_A
   set    IO_M_bar                to "1"
end vector

vector    IO_M_bar_low_Keep_on_Port_B
   initialize to Keep_on_Port_B
   set    IO_M_bar                to "0"
end vector


vector    IO_M_bar_high_keep_on_Port_B
   initialize to Keep_on_Port_B
   set    IO_M_bar                to "1"
end vector


vector    Read_bar_high_Keep_on_Port_A
   initialize to Keep_on_Port_A
   set    Read_bar                to "1"
end vector



vector    Read_bar_low_Keep_on_Port_A
   initialize to Keep_on_Port_A
   set    Read_bar                to "0"
end vector


vector    Read_bar_high_Keep_on_Port_B
   initialize to Keep_on_Port_B
   set    Read_bar                to "1"
end vector



vector    Read_bar_low_Keep_on_Port_B
   initialize to Keep_on_Port_B
   set    Read_bar                to "0"
end vector

vector    Read_bar_high
   initialize to Keep_on_Control_lines
   set    Read_bar                to "1"
end vector

vector    Read_bar_low
   initialize to Keep_on_Control_lines
   set    Read_bar                to "0"
end vector


vector    IO_Write_bar_low
   initialize to Keep_on_Data_lines
   set    IO_Write_bar            to "0"
end vector


vector    IO_Write_bar_high
   initialize to Keep_on_Data_lines
   set    IO_Write_bar            to "1"
end vector

vector    IO_Read_bar_high_keep_on_Port_A
   initialize to Keep_on_Port_A
   set    IO_Read_bar             to "1"
end vector

vector    IO_Read_bar_low_keep_on_Port_A
   initialize to Keep_on_Port_A
   set    IO_Read_bar             to "0"
end vector


vector    IO_Read_bar_high_keep_on_Port_B
   initialize to Keep_on_Port_B
   set    IO_Read_bar             to "1"
end vector

vector    IO_Read_bar_low_keep_on_Port_B
   initialize to Keep_on_Port_B
   set    IO_Read_bar             to "0"
end vector

vector    Out_mode
   initialize to Keep_on_control_lines
   drive  Data_bus
   set    Data_bus           to "FF"
end vector

vector    Drive_data_55
   initialize to Keep_on_control_lines
   drive  Data_bus
   set    Data_bus           to "55"
end vector


vector    Drive_data_66
   initialize to Keep_on_control_lines
   drive  Data_bus
   set    Data_bus           to "66"
end vector

vector    Drive_data_99
   initialize to Keep_on_control_lines
   drive  Data_bus
   set    Data_bus           to "99"
end vector

vector    Drive_data_AA
   initialize to Keep_on_control_lines
   drive  Data_bus
   set    Data_bus           to "AA"
end vector

vector    Recv_data_55_from_A
   initialize to Keep_on_Port_A
   receive  Data_bus
   set    Data_bus           to "55"
end vector

vector    Recv_data_AA_from_A
   initialize to Keep_on_Port_A
   receive  Data_bus
   set    Data_bus           to "AA"
end vector


vector    Recv_data_55_from_B
   initialize to Keep_on_Port_B
   receive  Data_bus
   set    Data_bus           to "55"
end vector

vector    Recv_data_AA_from_B
   initialize to Keep_on_Port_B
   receive  Data_bus
   set    Data_bus           to "AA"
end vector



vector    Recv_Port_A_AA
   initialize to Keep_on_control_lines
   receive Port_A
   set    Port_A                  to "AA"
end vector


vector    Recv_Port_A_55
   initialize to Keep_on_control_lines
   receive Port_A
   set    Port_A                  to "55"
end vector


vector    Recv_Port_B_AA
   initialize to Keep_on_control_lines
   receive Port_B
   set    Port_B                  to "AA"
end vector


vector    Recv_Port_B_55
   initialize to Keep_on_control_lines
   receive Port_B
   set    Port_B                  to "55"
end vector

vector    Recv_Port_A_66
   initialize to Keep_on_control_lines
   receive Port_A
   set    Port_A                  to "66"
end vector


vector    Recv_Port_A_99
   initialize to Keep_on_control_lines
   receive Port_A
   set    Port_A                  to "99"
end vector


vector    Recv_Port_B_66
   initialize to Keep_on_control_lines
   receive Port_B
   set    Port_B                  to "66"
end vector


vector    Recv_Port_B_99
   initialize to Keep_on_control_lines
   receive Port_B
   set    Port_B                  to "99"
end vector


vector   Drive_Port_A_AA
   initialize to Keep_on_control_lines
   drive  Port_A
   set    Port_A                  to "AA"
end vector


vector    Drive_Port_A_55
   initialize to Keep_on_control_lines
   drive Port_A
   set    Port_A                  to "55"
end vector


vector    Drive_Port_B_AA
   initialize to Keep_on_control_lines
   drive Port_B
   set    Port_B                  to "AA"
end vector


vector    Drive_Port_B_55
   initialize to Keep_on_control_lines
   drive Port_B
   set    Port_B                  to "55"
end vector


vector    Data_keeps
   initialize to Keep_on_control_lines
   receive  Data_bus
   set    Data_bus           to "KK"
end vector

vector    Address_counter
   drive Addr_bus
   set  Addr_bus            to   "000"
   upcounter         Addr_bus
end vector

vector    Address_counter_2
   drive Addr_bus
   set  Addr_bus         to   "500"
   upcounter         Addr_bus
end vector

!***************************************************************
!***************************************************************
!***************************************************************
sub   Initialize_device
   execute Normal_operation
   execute Reset_high
   repeat 2  times
      execute Clock_low
      execute Clock_high
   end repeat
   execute Reset_low
end sub


sub   IO_writing(Port_X_select,Drive_Data_XX, Recv_Port_X_XX)

   execute ALE_high
   execute Port_X_select
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute ALE_low_keep_AD1_2_lines
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute Drive_Data_XX
   execute Clock_low_Keep_on_Data_lines
   execute Clock_high_Keep_on_Data_lines
   execute IO_Write_bar_low

   repeat  2  times
   execute Clock_low_Keep_on_Data_lines
   execute Clock_high_Keep_on_Data_lines
   end repeat

   execute IO_Write_bar_high

   repeat 2 times
   execute Clock_low_Keep_on_Data_lines
   execute Clock_high_Keep_on_Data_lines
   end repeat

   execute Recv_Port_X_XX
end sub

sub   Port_A_reading(Port_X_select, Drive_Port_X_XX, Recv_Data_XX)

   execute ALE_high
   execute Port_X_select
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute ALE_low_keep_AD1_2_lines
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute Drive_Port_X_XX
   execute Clock_low_Keep_on_Port_A
   execute Clock_high_Keep_on_Port_A
   execute IO_Read_bar_low_Keep_on_Port_A

   execute Clock_low_Keep_on_Port_A
   execute Clock_high_Keep_on_Port_A

   execute Recv_Data_XX
   execute IO_Read_bar_high_keep_on_Port_A
end sub


sub   Port_B_reading(Port_X_select, Drive_Port_X_XX, Recv_Data_XX)

   execute ALE_high
   execute Port_X_select
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute ALE_low_keep_AD1_2_lines
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute Drive_Port_X_XX
   execute Clock_low_Keep_on_Port_B
   execute Clock_high_Keep_on_Port_B
   execute IO_Read_bar_low_Keep_on_Port_B

   execute Clock_low_Keep_on_Port_B
   execute Clock_high_Keep_on_Port_B

   execute Recv_Data_XX
   execute IO_Read_bar_high_keep_on_Port_B
end sub

sub   Read_Port_A(Port_X_select, Drive_Port_X_XX, Recv_Data_XX)

   execute ALE_high
   execute IO_M_bar_high
   execute Port_X_select
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute ALE_low_keep_AD1_2_lines
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute Drive_Port_X_XX
   execute Clock_low_Keep_on_Port_A
   execute Clock_high_Keep_on_Port_A
   execute Read_bar_low_Keep_on_Port_A

   execute Clock_low_Keep_on_Port_A
   execute Clock_high_Keep_on_Port_A

   execute Recv_Data_XX
   execute IO_M_bar_low_Keep_on_Port_A
   execute Read_bar_high_Keep_on_Port_A
end sub



sub   Read_Port_B(Port_X_select, Drive_Port_X_XX, Recv_Data_XX)

   execute ALE_high
   execute IO_M_bar_high
   execute Port_X_select
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute ALE_low_keep_AD1_2_lines
   execute Clock_low_Keep_on_AD1_2_lines
   execute Clock_high_Keep_on_AD1_2_lines
   execute Drive_Port_X_XX
   execute Clock_low_Keep_on_Port_B
   execute Clock_high_Keep_on_Port_B
   execute Read_bar_low_Keep_on_Port_B

   execute Clock_low_Keep_on_Port_B
   execute Clock_high_Keep_on_Port_B

   execute Recv_Data_XX
   execute IO_M_bar_low_Keep_on_Port_B
   execute Read_bar_high_Keep_on_Port_B
end sub

!***************************************************************
!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests.

unit "awaretest Test 1"
   call Initialize_device
   execute  Clock_high
   execute ALE_high
   execute Clock_low
   execute Clock_high
   execute ALE_low
   execute Clock_low
   execute Ready_low
   execute Clock_high
   execute Clock_low
   execute Ready_high
end unit

unit "awaretest Test 2"
!    This unit tests the response of a ROM against a
!    response learned from a known good device.
   call Initialize_device
   execute ALE_high
   execute IO_M_bar_low
   preset counter      Address_counter
   execute Clock_low_keep_on_Addr_lines
   execute Clock_high_keep_on_Addr_lines
   repeat            255   times
   execute ALE_low_keep_on_Addr_lines  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   execute Read_bar_low  compress
   execute Clock_low compress
   execute Clock_high  compress
   execute Data_keeps         compress
   execute Read_bar_high compress
   execute Clock_low compress
   execute Clock_high  compress
   execute ALE_high  compress
   execute IO_M_bar_low  compress
   count          Address_counter  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   end repeat
end unit

unit "PROM test 1"
!    This unit tests the response of a ROM against a
!    response learned from a known good device.
   call Initialize_device
   execute ALE_high
   execute IO_M_bar_low
   preset counter      Address_counter
   execute Clock_low_keep_on_Addr_lines
   execute Clock_high_keep_on_Addr_lines
   repeat              512  times
   execute ALE_low_keep_on_Addr_lines  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   execute Read_bar_low  compress
   execute Clock_low compress
   execute Clock_high  compress
   execute Data_keeps         compress
   execute Read_bar_high compress
   execute Clock_low compress
   execute Clock_high  compress
   execute ALE_high  compress
   execute IO_M_bar_low  compress
   count          Address_counter  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   end repeat
end unit


unit "PROM test 2"

!    This unit tests the response of a ROM against a
!    response learned from a known good device.
   call Initialize_device
   execute ALE_high
   execute IO_M_bar_low
   preset counter      Address_counter_2
   execute Clock_low_keep_on_Addr_lines
   execute Clock_high_keep_on_Addr_lines
   repeat              512  times
   execute ALE_low_keep_on_Addr_lines  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   execute Read_bar_low  compress
   execute Clock_low compress
   execute Clock_high  compress
   execute Data_keeps         compress
   execute Read_bar_high compress
   execute Clock_low compress
   execute Clock_high  compress
   execute ALE_high  compress
   execute IO_M_bar_low  compress
   count          Address_counter_2  compress
   execute Clock_low_keep_on_Addr_lines  compress
   execute Clock_high_keep_on_Addr_lines compress
   end repeat
end unit


unit "Chip enable inactive"

   call Initialize_device

   execute  Chip_enable_low
   execute  Clock_low
   execute  Clock_high
   call IO_Writing(Port_A_DDR_select,Out_mode,Clock_high)
   execute  Chip_enable_high
   execute  Clock_low
   execute  Clock_high
   call Port_A_Reading(Port_A_select,Drive_Port_A_55,Recv_Data_55_from_A)

end unit

unit "Chip enable bar inactive"

   call Initialize_device

   execute  Chip_enable_bar_high
   execute  Clock_low
   execute  Clock_high
   call IO_Writing(Port_A_DDR_select,Out_mode,Clock_high)
   execute  Chip_enable_bar_low
   execute  Clock_low
   execute  Clock_high
   call Port_A_Reading(Port_A_select,Drive_Port_A_55,Recv_Data_55_from_A)

end unit


unit  "Read Port A using Read_bar and IO_M_bar"

   call Initialize_device

   call Read_Port_A(Port_A_select, Drive_Port_A_55, Recv_Data_55_from_A)
   call Read_Port_A(Port_A_select, Drive_Port_A_AA, Recv_Data_AA_from_A)
   call Read_Port_A(Port_A_select, Drive_Port_A_55, Recv_Data_55_from_A)

end unit



unit  "Read Port B using Read_bar and IO_M_bar"

   call Initialize_device

   call Read_Port_B(Port_B_select, Drive_Port_B_55, Recv_Data_55_from_B)
   call Read_Port_B(Port_B_select, Drive_Port_B_AA, Recv_Data_AA_from_B)
   call Read_Port_B(Port_B_select, Drive_Port_B_55, Recv_Data_55_from_B)

end unit


unit "Ready"

   call Initialize_device
   execute  Clock_high
   execute ALE_high
   execute Clock_low
   execute Clock_high
   execute ALE_low
   execute Clock_low
   execute Ready_low
   execute Clock_high
   execute Clock_low
   execute Ready_high
end unit


unit  "Read Port A using IO_Read_bar"

   call Initialize_device

   call Port_A_Reading(Port_A_select, Drive_Port_A_55, Recv_Data_55_from_A)
   call Port_A_Reading(Port_A_select, Drive_Port_A_AA, Recv_Data_AA_from_A)
   call Port_A_Reading(Port_A_select, Drive_Port_A_55, Recv_Data_55_from_A)

end unit

unit  "Read Port B using IO_Read_bar"

   call Initialize_device

   call Port_B_Reading(Port_B_select,Drive_Port_B_AA,Recv_Data_AA_from_B)
   call Port_B_Reading(Port_B_select,Drive_Port_B_55,Recv_Data_55_from_B)
   call Port_B_Reading(Port_B_select,Drive_Port_B_AA,Recv_Data_AA_from_B)
end unit




unit  "Write to Port A "

   call Initialize_device

   call IO_Writing(Port_A_DDR_select,Out_mode,Clock_high)
   call IO_Writing(Port_A_select, Drive_Data_66, Recv_Port_A_66)
   call IO_Writing(Port_A_select, Drive_Data_99, Recv_Port_A_99)
   call IO_Writing(Port_A_select, Drive_Data_66, Recv_Port_A_66)

end unit


unit  "Write to Port B "

   call Initialize_device

   call IO_Writing(Port_B_DDR_select,Out_mode,Clock_high)
   call IO_Writing(Port_B_select, Drive_Data_99, Recv_Port_B_99)
   call IO_Writing(Port_B_select, Drive_Data_66, Recv_Port_B_66)
   call IO_Writing(Port_B_select, Drive_Data_99, Recv_Port_B_99)

end unit


unit   "Test Reset"

   call Initialize_device

   call IO_Writing(Port_A_DDR_select,Out_Mode,Clock_high)
   execute  Reset_high
   execute  Clock_low
   execute  Clock_high
   call Port_A_Reading(Port_A_select,Drive_Port_A_55,Recv_Data_55_from_A)

end unit





!    End of test