!!!!    6    0    1  991779191  V2a71                                         

! Device           : 74ls295
! Function         : shift_register 3-state 4-bit_bidirectional_universal
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign  VCC         to pins 14
assign  GND         to pins 7

assign  A_input     to pins 2
assign  B_input     to pins 3
assign  C_input     to pins 4
assign  D_input     to pins 5
assign  Parallel_inputs to pins 2,3,4,5
assign  Serial_input    to pins 1

assign  QA_output   to pins 13
assign  QB_output   to pins 12
assign  QC_output   to pins 11
assign  QD_output   to pins 10
assign  Outputs     to pins 13,12,11,10
assign  D0          to pins 10         !AT Added for minimum pin test.
assign  D1          to pins 11         !AT Added for minimum pin test.
assign  D2          to pins 12         !AT Added for minimum pin test.
assign  D3          to pins 13         !AT Added for minimum pin test.

assign  Clock       to pins 9
assign  Mode_input  to pins 6
assign  Output_enable to pins 8

family  TTL

power   VCC, GND

inputs  Parallel_inputs, Serial_input, Clock, Mode_input, Output_enable
inputs  A_input, B_input, C_input, D_input

outputs Outputs
outputs D0, D1, D2, D3          !AT Added for minimum pin test.

disable Outputs     with Output_enable  to    "0"

when Output_enable is "0" inactive Outputs

trace Outputs to  Parallel_inputs,Serial_input,Clock,Mode_input,Output_enable
!*********************************************************************
!*********************************************************************

vector    Clock_high
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
end vector

vector    Clock_low__D
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  D_input             to "k"
     set  Clock               to "0"
end vector

vector    Clock_low__load
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Parallel_inputs     to "kkkk"
     set  Clock               to "0"
end vector

vector    Clock_low__serial
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Serial_input        to "k"
     set  Clock               to "0"
end vector

vector    Clock_low__shift
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "0"
end vector

vector    D_input_high
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  D_input             to "1"
end vector

vector    D_input_low
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  D_input             to "0"
end vector

vector    Mode_low
     set  Clock               to "1"
     set  Mode_input          to "0"
end vector

vector    Outputs_0000
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Outputs             to "0000"
end vector

vector    Outputs_0000_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  Outputs             to "0000"
end vector

vector    Outputs_0101
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Outputs             to "0101"
end vector

vector    Outputs_1010
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Outputs             to "1010"
end vector

vector    Outputs_0101_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  Outputs             to "0101"
end vector

vector    Outputs_1010_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  Outputs             to "1010"
end vector

vector    Outputs_1111
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Outputs             to "1111"
end vector

vector    Outputs_1111_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  Outputs             to "1111"
end vector

vector    Outputs_X010
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "1"
     set  Outputs             to "X010"
end vector

vector    Outputs_XX01
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "1"
     set  Outputs             to "XX01"
end vector

vector    Outputs_XXX0
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "1"
     set  Outputs             to "XXX0"
end vector

vector    Parallel_inputs_0101
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "0101"
end vector

vector    Parallel_inputs_1010
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "1010"
end vector

vector    Parallel_inputs_0000
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "0000"
end vector

vector    Parallel_inputs_1111
     set  Output_enable       to "1"
     set  Mode_input          to "1"
     set  Clock               to "1"
     set  Parallel_inputs     to "1111"
end vector

vector    Serial_input_high
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "1"
     set  Serial_input        to "1"
end vector

vector    Serial_input_low
     set  Output_enable       to "1"
     set  Mode_input          to "0"
     set  Clock               to "1"
     set  Serial_input        to "0"
end vector




!*****VECTORS FOR DISABLE TESTS*****



vector    Outputs_0000_ksd_Disabled
     set  Output_enable       to "0"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  Outputs             to "0000"
end vector

vector    Outputs_1111_ksd_Disabled
     set  Output_enable       to "0"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  Outputs             to "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    D0_0_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D0                  to "0"
end vector

vector    D0_1_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D0                  to "1"
end vector

vector    D1_0_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D1                  to "0"
end vector

vector    D1_1_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D1                  to "1"
end vector

vector    D2_0_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D2                  to "0"
end vector

vector    D2_1_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D2                  to "1"
end vector

vector    D3_0_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D3                  to "0"
end vector

vector    D3_1_ksd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Serial_input        to "k"
     set  D3                  to "1"
end vector

vector    D0_0_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D0                  to "0"
end vector

vector    D0_1_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D0                  to "1"
end vector

vector    D1_0_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D1                  to "0"
end vector

vector    D1_1_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D1                  to "1"
end vector

vector    D2_0_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D2                  to "0"
end vector

vector    D2_1_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D2                  to "1"
end vector

vector    D3_0_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D3                  to "0"
end vector

vector    D3_1_kpd
     set  Output_enable       to "1"
     set  Mode_input          to "k"
     set  Clock               to "1"
     set  Parallel_inputs     to "kkkk"
     set  D3                  to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_low)
     execute   Clock_low
     execute   Clock_high

end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D0_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D0_1_ksd
end unit

unit "awaretest D1 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D1_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D1_1_ksd
end unit

unit "awaretest D2 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D2_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D2_1_ksd
end unit

unit "awaretest D3 serial input Test"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D3_0_ksd

     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   D3_1_ksd
end unit

unit "awaretest D0 parallel load Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_low__load)
     execute   D0_0_kpd
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_low__load)
     execute   D0_1_kpd
end unit

unit "awaretest D1 parallel load Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_low__load)
     execute   D1_0_kpd
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_low__load)
     execute   D1_1_kpd
end unit

unit "awaretest D2 parallel load Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_low__load)
     execute   D2_0_kpd
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_low__load)
     execute   D2_1_kpd
end unit

unit "awaretest D3 parallel load Test"
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_low__load)
     execute   D3_0_kpd
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_low__load)
     execute   D3_1_kpd
end unit

!****************************************************************

unit "test serial input"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_0000_ksd
     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_1111_ksd
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_0000_ksd
end unit

unit "test parallel inputs"
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_0101_kpd
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_1010_kpd
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_0101_kpd
end unit

unit "test parallel input, shift right"
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_0101_kpd
     execute   Mode_low
     call      Clock_cycle (Clock_low__shift)
     execute   Outputs_X010
     call      Clock_cycle (Clock_low__shift)
     execute   Outputs_XX01
     call      Clock_cycle (Clock_low__shift)
     execute   Outputs_XXX0
end unit

unit "test circular shift right"
     tied      Serial_input, QD_output
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_0101
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_1010
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_low__load)
     execute   Outputs_0101
     execute   Mode_low
     call      Clock_cycle (Clock_low__shift)
     execute   Outputs_1010
     call      Clock_cycle (Clock_low__shift)
     execute   Outputs_0101
end unit

unit "test shift left"
     tied      A_input, QB_output
     tied      B_input, QC_output
     tied      C_input, QD_output
     repeat    8 times
          execute   D_input_low
          call      Clock_cycle (Clock_low__D)
     end repeat
     execute   Outputs_0000
     repeat    4 times
          execute   D_input_high
          call      Clock_cycle (Clock_low__D)
     end repeat
     execute   Outputs_1111
     repeat    4 times
          execute   D_input_low
          call      Clock_cycle (Clock_low__D)
     end repeat
     execute   Outputs_0000
end unit




!*****TESTS FOR DISABLE **************************



unit disable test "Disable Test for serial input"
     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_0000_ksd_Disabled

     execute   Serial_input_low
     repeat    4 times
          execute   Serial_input_high
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_1111_ksd_Disabled

     repeat    4 times
          execute   Serial_input_low
          call      Clock_cycle (Clock_low__serial)
     end repeat
     execute   Outputs_0000_ksd_Disabled
end unit


!    End of test