!!!!    6    0    1  991779533  Vc5b0                                         

! Device           : 74hc195
! Function         : shift_register, 4-bit_parallel-in/out
! revision         : B.01.00
! safeguard        : standard_hcmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign   VCC         to pins 16
assign   GND         to pins 8

assign   Parallel_inputs  to pins 4,5,6,7
assign   Serial_inputs    to pins 2,3

assign   Outputs     to pins 15,14,13,12,11
assign   D0          to pins 11         !AT Added for minimum pin test.
assign   D1          to pins 12         !AT Added for minimum pin test.
assign   D2          to pins 13         !AT Added for minimum pin test.
assign   D3          to pins 14         !AT Added for minimum pin test.
assign   D4          to pins 15         !AT Added for minimum pin test.

assign   QD_output   to pins 12
assign   QD_bar_out  to pins 11

assign   Clock       to pins 10
assign   Shift_load  to pins 9
assign   Clear_bar   to pins 1

family   CMOS

power    VCC, GND

inputs   Parallel_inputs, Serial_inputs, Clock, Shift_load, Clear_bar

outputs  Outputs, QD_output, QD_bar_out
outputs D0, D1, D2, D3, D4      !AT Added for minimum pin test.

trace Outputs  to  Parallel_inputs, Serial_inputs, Clock, Shift_load, Clear_bar

!*********************************************************************
!*********************************************************************

vector  Clear_low
   set   Clock             to "0"
   set   Clear_bar         to "0"
   set   Outputs           to "00001"
end vector

vector  Clock_high__load
   set   Clear_bar         to "1"
   set   Shift_load        to "0"
   set   Parallel_inputs   to "kkkk"
   set   Clock             to "1"
end vector

vector  Clock_high__serial
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Serial_inputs     to "kk"
   set   Clock             to "1"
end vector

vector  Clock_high__shift
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "1"
end vector

vector  Clock_low
   set   Clear_bar         to "1"
   set   Shift_load        to "k"
   set   Clock             to "0"
end vector

vector  Outputs_00001
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "00001"
end vector

vector  Outputs_00001_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   Outputs           to "00001"
end vector

vector  Outputs_00101
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "00101"
end vector

vector  Outputs_01010
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "01010"
end vector

vector  Outputs_01101
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "01101"
end vector

vector  Outputs_10010
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "10010"
end vector

vector  Outputs_10101
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "10101"
end vector

vector  Outputs_11010
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "11010"
end vector

vector  Outputs_11110
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "11110"
end vector

vector  Outputs_11110_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "11"
   set   Outputs           to "11110"
end vector

vector  Outputs_X0101
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "X0101"
end vector

vector  Outputs_X1010
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "X1010"
end vector

vector  Outputs_XX010
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "XX010"
end vector

vector  Outputs_XX101
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "XX101"
end vector

vector  Outputs_XXX01
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "XXX01"
end vector

vector  Outputs_XXX10
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Outputs           to "XXX10"
end vector

vector  Parallel_inputs_0000
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "0"
   set   Parallel_inputs   to "0000"
end vector

vector  Parallel_inputs_0101
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "0"
   set   Parallel_inputs   to "0101"
end vector

vector  Parallel_inputs_1010
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "0"
   set   Parallel_inputs   to "1010"
end vector

vector  Parallel_inputs_1111
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "0"
   set   Parallel_inputs   to "1111"
end vector

vector  Serial_inputs_00
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "1"
   set   Serial_inputs     to "00"
end vector

vector  Serial_inputs_11
   set   Clear_bar         to "1"
   set   Clock             to "0"
   set   Shift_load        to "1"
   set   Serial_inputs     to "11"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  D0_0
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D0                to "0"
end vector

vector  D0_1
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D0                to "1"
end vector

vector  D1_0
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D1                to "0"
end vector

vector  D1_1
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D1                to "1"
end vector

vector  D2_0
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D2                to "0"
end vector

vector  D2_1
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D2                to "1"
end vector

vector  D3_0
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D3                to "0"
end vector

vector  D3_1
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D3                to "1"
end vector

vector  D4_0
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D4                to "0"
end vector

vector  D4_1
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   D4                to "1"
end vector

vector  D0_0_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D0                to "0"
end vector

vector  D0_1_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D0                to "1"
end vector

vector  D1_0_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D1                to "0"
end vector

vector  D1_1_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D1                to "1"
end vector

vector  D2_0_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D2                to "0"
end vector

vector  D2_1_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D2                to "1"
end vector

vector  D3_0_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D3                to "0"
end vector

vector  D3_1_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D3                to "1"
end vector

vector  D4_0_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D4                to "0"
end vector

vector  D4_1_ksd
   set   Clear_bar         to "1"
   set   Shift_load        to "1"
   set   Clock             to "0"
   set   Serial_inputs     to "kk"
   set   D4                to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_high)
   execute  Clock_high
   execute  Clock_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 shift Test"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D0_1_ksd

   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D0_0_ksd
end unit

unit "awaretest D1 shift Test"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D1_0_ksd

   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D1_1_ksd
end unit

unit "awaretest D2 shift Test"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D2_0_ksd

   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D2_1_ksd
end unit

unit "awaretest D3 shift Test"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D3_0_ksd

   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D3_1_ksd
end unit

unit "awaretest D4 shift Test"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D4_0_ksd

   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  D4_1_ksd
end unit

unit "awaretest D0 parallel load Test"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  D0_1

   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  D0_0
end unit

unit "awaretest D1 parallel load Test"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  D1_0

   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  D1_1
end unit

unit "awaretest D2 parallel load Test"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  D2_0

   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  D2_1
end unit

unit "awaretest D3 parallel load Test"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  D3_0

   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  D3_1
end unit

unit "awaretest D4 parallel load Test"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  D4_0

   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  D4_1
end unit

!****************************************************************

!    This test assumes that both the J and K_bar inputs are
!    controllable.

unit  "shift only, no clear"
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  Outputs_00001_ksd
   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  Outputs_11110_ksd
   repeat   4 times
      execute  Serial_inputs_00
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  Outputs_00001_ksd
end unit

unit  "parallel load"
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_00001
   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_11110
   execute  Parallel_inputs_0000
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_00001
end unit

unit  "parallel input, shift output"
   execute  Parallel_inputs_1010
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_10101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_X1010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_XX101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_XXX10
   execute  Parallel_inputs_0101
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_01010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_X0101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_XX010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_XXX01
end unit

unit  "test clear, parallel input"
   execute  Clear_low
   execute  Parallel_inputs_1111
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_11110
   execute  Clear_low
end unit

unit  "test clear, serial inputs"
   execute  Clear_low
   repeat   4 times
      execute  Serial_inputs_11
      call  Clock_cycle (Clock_high__serial)
   end repeat
   execute  Outputs_11110_ksd
   execute  Clear_low
end unit

unit  "circular shift, QD tied to J and K_bar"
   tied  Serial_inputs, QD_output
   execute  Parallel_inputs_1010
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_10101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_01010
   execute  Parallel_inputs_0101
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_01010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_10101
end unit

unit  "circular shift, QD_bar tied to J and K_bar"
   tied  Serial_inputs, QD_bar_out
   execute  Parallel_inputs_1010
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_10101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_11010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_01101
   execute  Parallel_inputs_0101
   call  Clock_cycle (Clock_high__load)
   execute  Outputs_01010
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_00101
   call  Clock_cycle (Clock_high__shift)
   execute  Outputs_10010
end unit

!    End of test