!!!!    6    0    1  992016854  Ve893                                         

! Device           : 29fct52
! Function         : 8-Bit Bidirectional Input/Output Port
! revision         : B.01.00
! safeguard        : high_out_mos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!
!  This test was developed in the pins free state.
!
sequential

vector cycle  500n
receive delay 400n

assign VCC    to pins "24"
assign GND    to pins "12"

assign A0         to pins "16"
assign A1         to pins "17"
assign A2         to pins "18"
assign A3         to pins "19"
assign A4         to pins "20"
assign A5         to pins "21"
assign A6         to pins "22"
assign A7         to pins "23"
assign Aside      to pins "16","17","18","19","20","21","22","23"

assign B0         to pins "8"
assign B1         to pins "7"
assign B2         to pins "6"
assign B3         to pins "5"
assign B4         to pins "4"
assign B5         to pins "3"
assign B6         to pins "2"
assign B7         to pins "1"
assign Bside      to pins "8","7","6","5","4","3","2","1"

assign OEAS_bar   to pins "15"
assign CPS        to pins "14"
assign CES_bar    to pins "13"

assign OEBR_bar   to pins "9"
assign CPR        to pins "10"
assign CER_bar    to pins "11"

family TTL

power  VCC, GND

inputs  OEAS_bar, CPS, CES_bar, OEBR_bar, CPR, CER_bar

bidirectional A0, A1, A2, A3, A4, A5, A6, A7
bidirectional B0, B1, B2, B3, B4, B5, B6, B7
bidirectional Aside, Bside

when OEAS_bar     is "1" inputs  Aside
when OEAS_bar     is "0" outputs Aside

when OEBR_bar     is "1" inputs  Bside
when OEBR_bar     is "0" outputs Bside

disable Aside                           with OEAS_bar to "1"
disable Bside                           with OEBR_bar to "1"
disable A0, A1, A2, A3, A4, A5, A6, A7  with OEAS_bar to "1"
disable B0, B1, B2, B3, B4, B5, B6, B7  with OEBR_bar to "1"

trace Bside       to Aside, OEBR_bar, CPR, CER_bar
trace Aside       to Bside, OEAS_bar, CPS, CES_bar
trace A0          to B0
trace A1          to B1
trace A2          to B2
trace A3          to B3
trace A4          to B4
trace A5          to B5
trace A6          to B6
trace A7          to B7
trace B0          to A0
trace B1          to A1
trace B2          to A2
trace B3          to A3
trace B4          to A4
trace B5          to A5
trace B6          to A6
trace B7          to A7


!*****************************************************************************!
!************************** Vector Defintion Section *************************!
!*****************************************************************************!

vector Initial_all
   set OEBR_bar     to  "1"
   set CER_bar      to  "1"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "1"
   set CPS          to  "1"
end vector

vector Initial_all_CERlow
   set OEBR_bar     to  "1"
   set CER_bar      to  "0"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "1"
   set CPS          to  "1"
end vector

vector Initial_all_CESlow
   set OEBR_bar     to  "1"
   set CER_bar      to  "1"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "0"
   set CPS          to  "1"
end vector

vector Initial_all_Renabl_low
   set OEBR_bar     to  "0"
   set CER_bar      to  "0"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "1"
   set CPS          to  "1"
end vector

vector Initial_all_Senabl_low
   set OEBR_bar     to  "1"
   set CER_bar      to  "1"
   set CPR          to  "1"
   set OEAS_bar     to  "0"
   set CES_bar      to  "0"
   set CPS          to  "1"
end vector

vector Initial_R
   set OEBR_bar     to  "1"
   set CER_bar      to  "1"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
end vector

vector Initial_R_0EBR_bar_low
   set OEBR_bar     to  "0"
   set CER_bar      to  "1"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
end vector

vector Initial_R_CER_bar_low
   set OEBR_bar     to  "1"
   set CER_bar      to  "0"
   set CPR          to  "1"
   set OEAS_bar     to  "1"
end vector

vector Initial_S
   set OEBR_bar     to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "1"
   set CPS          to  "1"
end vector

vector Initial_S_0EAS_bar_low
   set OEBR_bar     to  "1"
   set OEAS_bar     to  "0"
   set CER_bar      to  "1"
   set CPR          to  "1"
end vector

vector Initial_S_CES_bar_low
   set OEBR_bar     to  "1"
   set OEAS_bar     to  "1"
   set CES_bar      to  "0"
   set CPS          to  "1"
end vector

vector Keep_states_all
   set OEBR_bar     to  "k"
   set CER_bar      to  "k"
   set CPR          to  "k"
   set OEAS_bar     to  "k"
   set CES_bar      to  "k"
   set CPS          to  "k"
end vector

vector Keep_states_R
   set OEBR_bar     to  "k"
   set CER_bar      to  "k"
   set CPR          to  "k"
   set OEAS_bar     to  "k"
end vector

vector Keep_states_S
   set OEBR_bar     to  "k"
   set OEAS_bar     to  "k"
   set CES_bar      to  "k"
   set CPS          to  "k"
end vector

vector Keep_Rinputs_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "kkkkkkkk"
end vector

vector Keep_Rinputs
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "kkkkkkkk"
end vector

vector Keep_Sinputs_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "kkkkkkkk"
end vector

vector Keep_Sinputs
   initialize       to  Keep_states_S
   drive            Bside
   set Bside        to  "kkkkkkkk"
end vector

vector Rreg_latch_all
   initialize       to  Keep_Rinputs_all
   set CPR          to  "1"
end vector

vector Rreg_latch
   initialize       to  Keep_Rinputs
   set CPR          to  "1"
end vector

vector Clock_latch_S
   initialize       to  Keep_states_all
   set CPS          to  "1"
end vector

vector Clock_latch_R
   initialize       to  Keep_states_all
   set CPR          to  "1"
end vector

vector RegisterR_output_enable
   initialize       to  Keep_states_all
   set OEBR_bar     to  "0"
end vector

vector RegisterR_output_disabled
   initialize       to  Keep_states_all
   set OEBR_bar     to  "1"
end vector

vector RegisterS_output_enable
   initialize       to  Keep_states_all
   set OEAS_bar     to  "0"
end vector

vector RegisterS_output_disabled
   initialize       to  Keep_states_all
   set OEAS_bar     to  "1"
end vector

vector Rreg_clk_disable
   initialize       to  Keep_states_R
   set CER_bar      to  "1"
end vector

vector Sreg_clk_disable
   initialize       to  Keep_states_R
   set CES_bar      to  "1"
end vector

vector Sreg_latch_all
   initialize       to  Keep_Sinputs_all
   set CPS          to  "1"
end vector

vector Sreg_latch
   initialize       to  Keep_Sinputs
   set CPS          to  "1"
end vector

vector Rreg_enable_all
   initialize       to  Keep_states_all
   set CER_bar      to  "0"
end vector

vector Rreg_enable
   initialize       to  Keep_states_R
   set CER_bar      to  "0"
end vector

vector Sreg_enable_all
   initialize       to  Keep_states_all
   set CES_bar      to  "0"
end vector

vector Sreg_enable
   initialize       to  Keep_states_S
   set CES_bar      to  "0"
end vector

vector Rreg_clk_low_all
   initialize       to  Keep_states_all
   set CPR          to  "0"
end vector

vector Rreg_clk_low
   initialize       to  Keep_states_R
   set CPR          to  "0"
end vector

vector Sreg_clk_low_all
   initialize       to  Keep_states_all
   set CPS          to  "0"
end vector

vector Sreg_clk_low
   initialize       to  Keep_states_S
   set CPS          to  "0"
end vector

vector InputR_10101010_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "10101010"
end vector

vector InputR_10101010
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "10101010"
end vector

vector InputR_01010101_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "01010101"
end vector

vector InputR_01010101
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "01010101"
end vector

vector InputR_10010010_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "10010010"
end vector

vector InputR_10010010
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "10010010"
end vector

vector InputR_00100100_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "00100100"
end vector

vector InputR_00100100
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "00100100"
end vector

vector InputR_10001000_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "10001000"
end vector

vector InputR_10001000
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "10001000"
end vector

vector InputR_00010001_all
   initialize       to  Keep_states_all
   drive            Aside
   set Aside        to  "00010001"
end vector

vector InputR_00010001
   initialize       to  Keep_states_R
   drive            Aside
   set Aside        to  "00010001"
end vector

vector InputS_10101010_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "10101010"
end vector

vector InputS_10101010
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "10101010"
end vector

vector InputS_01010101_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "01010101"
end vector

vector InputS_01010101
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "01010101"
end vector

vector InputS_10010010_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "10010010"
end vector

vector InputS_10010010
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "10010010"
end vector

vector InputS_00100100_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "00100100"
end vector

vector InputS_00100100
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "00100100"
end vector

vector InputS_10001000_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "10001000"
end vector

vector InputS_10001000
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "10001000"
end vector

vector InputS_00010001_all
   initialize       to  Keep_states_all
   drive            Bside
   set Bside        to  "00010001"
end vector

vector InputS_00010001
   initialize       to  Keep_states_R
   drive            Bside
   set Bside        to  "00010001"
end vector

vector OutputR_enab_all
   initialize       to  Keep_states_all
   set OEBR_bar     to  "0"
end vector

vector OutputR_enab
   initialize       to  Keep_states_R
   set OEBR_bar     to  "0"
end vector

vector OutputS_enab_all
   initialize       to  Keep_states_all
   set OEAS_bar     to  "0"
end vector

vector OutputS_enab
   initialize       to  Keep_states_R
   set OEAS_bar     to  "0"
end vector

vector OutputR_10101010_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "10101010"
end vector

vector OutputR_10101010
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "10101010"
end vector

vector OutputR_01010101_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "01010101"
end vector

vector OutputR_01010101
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "01010101"
end vector

vector OutputR_10010010_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "10010010"
end vector

vector OutputR_10010010
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "10010010"
end vector

vector OutputR_00100100_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "00100100"
end vector

vector OutputR_00100100
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "00100100"
end vector

vector OutputR_10001000_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "10001000"
end vector

vector OutputR_10001000
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "10001000"
end vector

vector OutputR_00010001_all
   initialize       to  OutputR_enab_all
   receive          Bside
   set Bside        to  "00010001"
end vector

vector OutputR_00010001
   initialize       to  OutputR_enab
   receive          Bside
   set Bside        to  "00010001"
end vector

vector OutputS_10101010_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "10101010"
end vector

vector OutputS_10101010
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "10101010"
end vector

vector OutputS_01010101_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "01010101"
end vector

vector OutputS_01010101
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "01010101"
end vector

vector OutputS_10010010_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "10010010"
end vector

vector OutputS_10010010
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "10010010"
end vector

vector OutputS_00100100_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "00100100"
end vector

vector OutputS_00100100
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "00100100"
end vector

vector OutputS_10001000_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "10001000"
end vector

vector OutputS_10001000
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "10001000"
end vector

vector OutputS_00010001_all
   initialize       to  OutputS_enab_all
   receive          Aside
   set Aside        to  "00010001"
end vector

vector OutputS_00010001
   initialize       to  OutputS_enab
   receive          Aside
   set Aside        to  "00010001"
end vector

vector InputA0_high
   initialize       to  Keep_states_R
   drive            Aside
   set A0           to  "1"
end vector

vector InputA0_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A0           to  "1"
end vector

vector InputA1_high
   initialize       to  Keep_states_R
   drive            Aside
   set A1           to  "1"
end vector

vector InputA1_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A1           to  "1"
end vector

vector InputA2_high
   initialize       to  Keep_states_R
   drive            Aside
   set A2           to  "1"
end vector

vector InputA2_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A2           to  "1"
end vector

vector InputA3_high
   initialize       to  Keep_states_R
   drive            Aside
   set A3           to  "1"
end vector

vector InputA3_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A3           to  "1"
end vector

vector InputA4_high
   initialize       to  Keep_states_R
   drive            Aside
   set A4           to  "1"
end vector

vector InputA4_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A4           to  "1"
end vector

vector InputA5_high
   initialize       to  Keep_states_R
   drive            Aside
   set A5           to  "1"
end vector

vector InputA5_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A5           to  "1"
end vector

vector InputA6_high
   initialize       to  Keep_states_R
   drive            Aside
   set A6           to  "1"
end vector

vector InputA6_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A6           to  "1"
end vector

vector InputA7_high
   initialize       to  Keep_states_R
   drive            Aside
   set A7           to  "1"
end vector

vector InputA7_high_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A7           to  "1"
end vector

vector InputA0_low
   initialize       to  Keep_states_R
   drive            Aside
   set A0           to  "0"
end vector

vector InputA0_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A0           to  "0"
end vector

vector InputA1_low
   initialize       to  Keep_states_R
   drive            Aside
   set A1           to  "0"
end vector

vector InputA1_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A1           to  "0"
end vector

vector InputA2_low
   initialize       to  Keep_states_R
   drive            Aside
   set A2           to  "0"
end vector

vector InputA2_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A2           to  "0"
end vector

vector InputA3_low
   initialize       to  Keep_states_R
   drive            Aside
   set A3           to  "0"
end vector

vector InputA3_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A3           to  "0"
end vector

vector InputA4_low
   initialize       to  Keep_states_R
   drive            Aside
   set A4           to  "0"
end vector

vector InputA4_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A4           to  "0"
end vector

vector InputA5_low
   initialize       to  Keep_states_R
   drive            Aside
   set A5           to  "0"
end vector

vector InputA5_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A5           to  "0"
end vector

vector InputA6_low
   initialize       to  Keep_states_R
   drive            Aside
   set A6           to  "0"
end vector

vector InputA6_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A6           to  "0"
end vector

vector InputA7_low
   initialize       to  Keep_states_R
   drive            Aside
   set A7           to  "0"
end vector

vector InputA7_low_rvrse
   initialize       to  Keep_states_all
   drive            Aside
   set A7           to  "0"
end vector

vector InputB0_high
   initialize       to  Keep_states_S
   drive            Bside
   set B0           to  "1"
end vector

vector InputB0_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B0           to  "1"
end vector

vector InputB1_high
   initialize       to  Keep_states_S
   drive            Bside
   set B1           to  "1"
end vector

vector InputB1_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B1           to  "1"
end vector

vector InputB2_high
   initialize       to  Keep_states_S
   drive            Bside
   set B2           to  "1"
end vector

vector InputB2_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B2           to  "1"
end vector

vector InputB3_high
   initialize       to  Keep_states_S
   drive            Bside
   set B3           to  "1"
end vector

vector InputB3_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B3           to  "1"
end vector

vector InputB4_high
   initialize       to  Keep_states_S
   drive            Bside
   set B4           to  "1"
end vector

vector InputB4_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B4           to  "1"
end vector

vector InputB5_high
   initialize       to  Keep_states_S
   drive            Bside
   set B5           to  "1"
end vector

vector InputB5_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B5           to  "1"
end vector

vector InputB6_high
   initialize       to  Keep_states_S
   drive            Bside
   set B6           to  "1"
end vector

vector InputB6_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B6           to  "1"
end vector

vector InputB7_high
   initialize       to  Keep_states_S
   drive            Bside
   set B7           to  "1"
end vector

vector InputB7_high_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B7           to  "1"
end vector

vector InputB0_low
   initialize       to  Keep_states_S
   drive            Bside
   set B0           to  "0"
end vector

vector InputB0_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B0           to  "0"
end vector

vector InputB1_low
   initialize       to  Keep_states_S
   drive            Bside
   set B1           to  "0"
end vector

vector InputB1_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B1           to  "0"
end vector

vector InputB2_low
   initialize       to  Keep_states_S
   drive            Bside
   set B2           to  "0"
end vector

vector InputB2_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B2           to  "0"
end vector

vector InputB3_low
   initialize       to  Keep_states_S
   drive            Bside
   set B3           to  "0"
end vector

vector InputB3_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B3           to  "0"
end vector

vector InputB4_low
   initialize       to  Keep_states_S
   drive            Bside
   set B4           to  "0"
end vector

vector InputB4_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B4           to  "0"
end vector

vector InputB5_low
   initialize       to  Keep_states_S
   drive            Bside
   set B5           to  "0"
end vector

vector InputB5_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B5           to  "0"
end vector

vector InputB6_low
   initialize       to  Keep_states_S
   drive            Bside
   set B6           to  "0"
end vector

vector InputB6_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B6           to  "0"
end vector

vector InputB7_low
   initialize       to  Keep_states_S
   drive            Bside
   set B7           to  "0"
end vector

vector InputB7_low_rvrse
   initialize       to  Keep_states_all
   drive            Bside
   set B7           to  "0"
end vector

vector OutputB0_high
   initialize       to  OutputR_enab
   receive          Bside
   set B0           to  "1"
end vector

vector OutputB0_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B0           to  "1"
end vector

vector OutputB0_low
   initialize       to  OutputR_enab
   receive          Bside
   set B0           to  "0"
end vector

vector OutputB0_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B0           to  "0"
end vector

vector OutputB1_high
   initialize       to  OutputR_enab
   receive          Bside
   set B1           to  "1"
end vector

vector OutputB1_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B1           to  "1"
end vector

vector OutputB1_low
   initialize       to  OutputR_enab
   receive          Bside
   set B1           to  "0"
end vector

vector OutputB1_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B1           to  "0"
end vector

vector OutputB2_high
   initialize       to  OutputR_enab
   receive          Bside
   set B2           to  "1"
end vector

vector OutputB2_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B2           to  "1"
end vector

vector OutputB2_low
   initialize       to  OutputR_enab
   receive          Bside
   set B2           to  "0"
end vector

vector OutputB2_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B2           to  "0"
end vector

vector OutputB3_high
   initialize       to  OutputR_enab
   receive          Bside
   set B3           to  "1"
end vector

vector OutputB3_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B3           to  "1"
end vector

vector OutputB3_low
   initialize       to  OutputR_enab
   receive          Bside
   set B3           to  "0"
end vector

vector OutputB3_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B3           to  "0"
end vector

vector OutputB4_high
   initialize       to  OutputR_enab
   receive          Bside
   set B4           to  "1"
end vector

vector OutputB4_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B4           to  "1"
end vector

vector OutputB4_low
   initialize       to  OutputR_enab
   receive          Bside
   set B4           to  "0"
end vector

vector OutputB4_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B4           to  "0"
end vector

vector OutputB5_high
   initialize       to  OutputR_enab
   receive          Bside
   set B5           to  "1"
end vector

vector OutputB5_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B5           to  "1"
end vector

vector OutputB5_low
   initialize       to  OutputR_enab
   receive          Bside
   set B5           to  "0"
end vector

vector OutputB5_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B5           to  "0"
end vector

vector OutputB6_high
   initialize       to  OutputR_enab
   receive          Bside
   set B6           to  "1"
end vector

vector OutputB6_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B6           to  "1"
end vector

vector OutputB6_low
   initialize       to  OutputR_enab
   receive          Bside
   set B6           to  "0"
end vector

vector OutputB6_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B6           to  "0"
end vector

vector OutputB7_high
   initialize       to  OutputR_enab
   receive          Bside
   set B7           to  "1"
end vector

vector OutputB7_high_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B7           to  "1"
end vector

vector OutputB7_low
   initialize       to  OutputR_enab
   receive          Bside
   set B7           to  "0"
end vector

vector OutputB7_low_rvrse
   initialize       to  OutputR_enab_all
   receive          Bside
   set B7           to  "0"
end vector

vector OutputA0_high
   initialize       to  OutputS_enab
   receive          Aside
   set A0           to  "1"
end vector

vector OutputA0_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A0           to  "1"
end vector

vector OutputA0_low
   initialize       to  OutputS_enab
   receive          A0
   set A0           to  "0"
end vector

vector OutputA0_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A0           to  "0"
end vector

vector OutputA1_high
   initialize       to  OutputS_enab
   receive          Aside
   set A1           to  "1"
end vector

vector OutputA1_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A1           to  "1"
end vector

vector OutputA1_low
   initialize       to  OutputS_enab
   receive          Aside
   set A1           to  "0"
end vector

vector OutputA1_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A1           to  "0"
end vector

vector OutputA2_high
   initialize       to  OutputS_enab
   receive          Aside
   set A2           to  "1"
end vector

vector OutputA2_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A2           to  "1"
end vector

vector OutputA2_low
   initialize       to  OutputS_enab
   receive          Aside
   set A2           to  "0"
end vector

vector OutputA2_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A2           to  "0"
end vector

vector OutputA3_high
   initialize       to  OutputS_enab
   receive          Aside
   set A3           to  "1"
end vector

vector OutputA3_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A3           to  "1"
end vector

vector OutputA3_low
   initialize       to  OutputS_enab
   receive          Aside
   set A3           to  "0"
end vector

vector OutputA3_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A3           to  "0"
end vector

vector OutputA4_high
   initialize       to  OutputS_enab
   receive          Aside
   set A4           to  "1"
end vector

vector OutputA4_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A4           to  "1"
end vector

vector OutputA4_low
   initialize       to  OutputS_enab
   receive          Aside
   set A4           to  "0"
end vector

vector OutputA4_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A4           to  "0"
end vector

vector OutputA5_high
   initialize       to  OutputS_enab
   receive          Aside
   set A5           to  "1"
end vector

vector OutputA5_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A5           to  "1"
end vector

vector OutputA5_low
   initialize       to  OutputS_enab
   receive          Aside
   set A5           to  "0"
end vector

vector OutputA5_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A5           to  "0"
end vector

vector OutputA6_high
   initialize       to  OutputS_enab
   receive          Aside
   set A6           to  "1"
end vector

vector OutputA6_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A6           to  "1"
end vector

vector OutputA6_low
   initialize       to  OutputS_enab
   receive          Aside
   set A6           to  "0"
end vector

vector OutputA6_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A6           to  "0"
end vector

vector OutputA7_high
   initialize       to  OutputS_enab
   receive          Aside
   set A7           to  "1"
end vector

vector OutputA7_high_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A7           to  "1"
end vector

vector OutputA7_low
   initialize       to  OutputS_enab
   receive          Aside
   set A7           to  "0"
end vector

vector OutputA7_low_rvrse
   initialize       to  OutputS_enab_all
   receive          Aside
   set A7           to  "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector Keep_Rinput_A0
   initialize       to  Keep_states_R
   drive            A0
   set A0           to  "k"
end vector

vector Rreg_latch_A0
   initialize       to  Keep_Rinput_A0
   set CPR          to  "1"
end vector

vector Keep_Rinput_A1
   initialize       to  Keep_states_R
   drive            A1
   set A1           to  "k"
end vector

vector Rreg_latch_A1
   initialize       to  Keep_Rinput_A1
   set CPR          to  "1"
end vector

vector Keep_Rinput_A2
   initialize       to  Keep_states_R
   drive            A2
   set A2           to  "k"
end vector

vector Rreg_latch_A2
   initialize       to  Keep_Rinput_A2
   set CPR          to  "1"
end vector

vector Keep_Rinput_A3
   initialize       to  Keep_states_R
   drive            A3
   set A3           to  "k"
end vector

vector Rreg_latch_A3
   initialize       to  Keep_Rinput_A3
   set CPR          to  "1"
end vector

vector Keep_Rinput_A4
   initialize       to  Keep_states_R
   drive            A4
   set A4           to  "k"
end vector

vector Rreg_latch_A4
   initialize       to  Keep_Rinput_A4
   set CPR          to  "1"
end vector

vector Keep_Rinput_A5
   initialize       to  Keep_states_R
   drive            A5
   set A5           to  "k"
end vector

vector Rreg_latch_A5
   initialize       to  Keep_Rinput_A5
   set CPR          to  "1"
end vector

vector Keep_Rinput_A6
   initialize       to  Keep_states_R
   drive            A6
   set A6           to  "k"
end vector

vector Rreg_latch_A6
   initialize       to  Keep_Rinput_A6
   set CPR          to  "1"
end vector

vector Keep_Rinput_A7
   initialize       to  Keep_states_R
   drive            A7
   set A7           to  "k"
end vector

vector Rreg_latch_A7
   initialize       to  Keep_Rinput_A7
   set CPR          to  "1"
end vector

vector InputA0_high_A0
   initialize       to  Keep_states_R
   drive            A0
   set A0           to  "1"
end vector

vector InputA0_high_rvrse_A0
   initialize       to  Keep_states_all
   drive            A0
   set A0           to  "1"
end vector

vector InputA0_low_A0
   initialize       to  Keep_states_R
   drive            A0
   set A0           to  "0"
end vector

vector InputA0_low_rvrse_A0
   initialize       to  Keep_states_all
   drive            A0
   set A0           to  "0"
end vector

vector OutputA0_high_A0
   initialize       to  OutputS_enab
   receive          A0
   set A0           to  "1"
end vector

vector OutputA0_high_rvrse_A0
   initialize       to  OutputS_enab_all
   receive          A0
   set A0           to  "1"
end vector

vector OutputA0_low_A0
   initialize       to  OutputS_enab
   receive          A0
   set A0           to  "0"
end vector

vector OutputA0_low_rvrse_A0
   initialize       to  OutputS_enab_all
   receive          A0
   set A0           to  "0"
end vector

vector InputA1_high_A1
   initialize       to  Keep_states_R
   drive            A1
   set A1           to  "1"
end vector

vector InputA1_high_rvrse_A1
   initialize       to  Keep_states_all
   drive            A1
   set A1           to  "1"
end vector

vector InputA1_low_A1
   initialize       to  Keep_states_R
   drive            A1
   set A1           to  "0"
end vector

vector InputA1_low_rvrse_A1
   initialize       to  Keep_states_all
   drive            A1
   set A1           to  "0"
end vector

vector OutputA1_high_A1
   initialize       to  OutputS_enab
   receive          A1
   set A1           to  "1"
end vector

vector OutputA1_high_rvrse_A1
   initialize       to  OutputS_enab_all
   receive          A1
   set A1           to  "1"
end vector

vector OutputA1_low_A1
   initialize       to  OutputS_enab
   receive          A1
   set A1           to  "0"
end vector

vector OutputA1_low_rvrse_A1
   initialize       to  OutputS_enab_all
   receive          A1
   set A1           to  "0"
end vector

vector InputA2_high_A2
   initialize       to  Keep_states_R
   drive            A2
   set A2           to  "1"
end vector

vector InputA2_high_rvrse_A2
   initialize       to  Keep_states_all
   drive            A2
   set A2           to  "1"
end vector

vector InputA2_low_A2
   initialize       to  Keep_states_R
   drive            A2
   set A2           to  "0"
end vector

vector InputA2_low_rvrse_A2
   initialize       to  Keep_states_all
   drive            A2
   set A2           to  "0"
end vector

vector OutputA2_high_A2
   initialize       to  OutputS_enab
   receive          A2
   set A2           to  "1"
end vector

vector OutputA2_high_rvrse_A2
   initialize       to  OutputS_enab_all
   receive          A2
   set A2           to  "1"
end vector

vector OutputA2_low_A2
   initialize       to  OutputS_enab
   receive          A2
   set A2           to  "0"
end vector

vector OutputA2_low_rvrse_A2
   initialize       to  OutputS_enab_all
   receive          A2
   set A2           to  "0"
end vector

vector InputA3_high_A3
   initialize       to  Keep_states_R
   drive            A3
   set A3           to  "1"
end vector

vector InputA3_high_rvrse_A3
   initialize       to  Keep_states_all
   drive            A3
   set A3           to  "1"
end vector

vector InputA3_low_A3
   initialize       to  Keep_states_R
   drive            A3
   set A3           to  "0"
end vector

vector InputA3_low_rvrse_A3
   initialize       to  Keep_states_all
   drive            A3
   set A3           to  "0"
end vector

vector OutputA3_high_A3
   initialize       to  OutputS_enab
   receive          A3
   set A3           to  "1"
end vector

vector OutputA3_high_rvrse_A3
   initialize       to  OutputS_enab_all
   receive          A3
   set A3           to  "1"
end vector

vector OutputA3_low_A3
   initialize       to  OutputS_enab
   receive          A3
   set A3           to  "0"
end vector

vector OutputA3_low_rvrse_A3
   initialize       to  OutputS_enab_all
   receive          A3
   set A3           to  "0"
end vector

vector InputA4_high_A4
   initialize       to  Keep_states_R
   drive            A4
   set A4           to  "1"
end vector

vector InputA4_high_rvrse_A4
   initialize       to  Keep_states_all
   drive            A4
   set A4           to  "1"
end vector

vector InputA4_low_A4
   initialize       to  Keep_states_R
   drive            A4
   set A4           to  "0"
end vector

vector InputA4_low_rvrse_A4
   initialize       to  Keep_states_all
   drive            A4
   set A4           to  "0"
end vector

vector OutputA4_high_A4
   initialize       to  OutputS_enab
   receive          A4
   set A4           to  "1"
end vector

vector OutputA4_high_rvrse_A4
   initialize       to  OutputS_enab_all
   receive          A4
   set A4           to  "1"
end vector

vector OutputA4_low_A4
   initialize       to  OutputS_enab
   receive          A4
   set A4           to  "0"
end vector

vector OutputA4_low_rvrse_A4
   initialize       to  OutputS_enab_all
   receive          A4
   set A4           to  "0"
end vector

vector InputA5_high_A5
   initialize       to  Keep_states_R
   drive            A5
   set A5           to  "1"
end vector

vector InputA5_high_rvrse_A5
   initialize       to  Keep_states_all
   drive            A5
   set A5           to  "1"
end vector

vector InputA5_low_A5
   initialize       to  Keep_states_R
   drive            A5
   set A5           to  "0"
end vector

vector InputA5_low_rvrse_A5
   initialize       to  Keep_states_all
   drive            A5
   set A5           to  "0"
end vector

vector OutputA5_high_A5
   initialize       to  OutputS_enab
   receive          A5
   set A5           to  "1"
end vector

vector OutputA5_high_rvrse_A5
   initialize       to  OutputS_enab_all
   receive          A5
   set A5           to  "1"
end vector

vector OutputA5_low_A5
   initialize       to  OutputS_enab
   receive          A5
   set A5           to  "0"
end vector

vector OutputA5_low_rvrse_A5
   initialize       to  OutputS_enab_all
   receive          A5
   set A5           to  "0"
end vector

vector InputA6_high_A6
   initialize       to  Keep_states_R
   drive            A6
   set A6           to  "1"
end vector

vector InputA6_high_rvrse_A6
   initialize       to  Keep_states_all
   drive            A6
   set A6           to  "1"
end vector

vector InputA6_low_A6
   initialize       to  Keep_states_R
   drive            A6
   set A6           to  "0"
end vector

vector InputA6_low_rvrse_A6
   initialize       to  Keep_states_all
   drive            A6
   set A6           to  "0"
end vector

vector OutputA6_high_A6
   initialize       to  OutputS_enab
   receive          A6
   set A6           to  "1"
end vector

vector OutputA6_high_rvrse_A6
   initialize       to  OutputS_enab_all
   receive          A6
   set A6           to  "1"
end vector

vector OutputA6_low_A6
   initialize       to  OutputS_enab
   receive          A6
   set A6           to  "0"
end vector

vector OutputA6_low_rvrse_A6
   initialize       to  OutputS_enab_all
   receive          A6
   set A6           to  "0"
end vector

vector InputA7_high_A7
   initialize       to  Keep_states_R
   drive            A7
   set A7           to  "1"
end vector

vector InputA7_high_rvrse_A7
   initialize       to  Keep_states_all
   drive            A7
   set A7           to  "1"
end vector

vector InputA7_low_A7
   initialize       to  Keep_states_R
   drive            A7
   set A7           to  "0"
end vector

vector InputA7_low_rvrse_A7
   initialize       to  Keep_states_all
   drive            A7
   set A7           to  "0"
end vector

vector OutputA7_high_A7
   initialize       to  OutputS_enab
   receive          A7
   set A7           to  "1"
end vector

vector OutputA7_high_rvrse_A7
   initialize       to  OutputS_enab_all
   receive          A7
   set A7           to  "1"
end vector

vector OutputA7_low_A7
   initialize       to  OutputS_enab
   receive          A7
   set A7           to  "0"
end vector

vector OutputA7_low_rvrse_A7
   initialize       to  OutputS_enab_all
   receive          A7
   set A7           to  "0"
end vector

vector Keep_Sinput_B0
   initialize       to  Keep_states_S
   drive            B0
   set B0           to  "k"
end vector

vector Sreg_latch_B0
   initialize       to  Keep_Sinput_B0
   set CPS          to  "1"
end vector

vector Keep_Sinput_B1
   initialize       to  Keep_states_S
   drive            B1
   set B1           to  "k"
end vector

vector Sreg_latch_B1
   initialize       to  Keep_Sinput_B1
   set CPS          to  "1"
end vector

vector Keep_Sinput_B2
   initialize       to  Keep_states_S
   drive            B2
   set B2           to  "k"
end vector

vector Sreg_latch_B2
   initialize       to  Keep_Sinput_B2
   set CPS          to  "1"
end vector

vector Keep_Sinput_B3
   initialize       to  Keep_states_S
   drive            B3
   set B3           to  "k"
end vector

vector Sreg_latch_B3
   initialize       to  Keep_Sinput_B3
   set CPS          to  "1"
end vector

vector Keep_Sinput_B4
   initialize       to  Keep_states_S
   drive            B4
   set B4           to  "k"
end vector

vector Sreg_latch_B4
   initialize       to  Keep_Sinput_B4
   set CPS          to  "1"
end vector

vector Keep_Sinput_B5
   initialize       to  Keep_states_S
   drive            B5
   set B5           to  "k"
end vector

vector Sreg_latch_B5
   initialize       to  Keep_Sinput_B5
   set CPS          to  "1"
end vector

vector Keep_Sinput_B6
   initialize       to  Keep_states_S
   drive            B6
   set B6           to  "k"
end vector

vector Sreg_latch_B6
   initialize       to  Keep_Sinput_B6
   set CPS          to  "1"
end vector

vector Keep_Sinput_B7
   initialize       to  Keep_states_S
   drive            B7
   set B7           to  "k"
end vector

vector Sreg_latch_B7
   initialize       to  Keep_Sinput_B7
   set CPS          to  "1"
end vector

vector InputB0_high_B0
   initialize       to  Keep_states_S
   drive            B0
   set B0           to  "1"
end vector

vector InputB0_high_rvrse_B0
   initialize       to  Keep_states_all
   drive            B0
   set B0           to  "1"
end vector

vector InputB0_low_B0
   initialize       to  Keep_states_S
   drive            B0
   set B0           to  "0"
end vector

vector InputB0_low_rvrse_B0
   initialize       to  Keep_states_all
   drive            B0
   set B0           to  "0"
end vector

vector OutputB0_high_B0
   initialize       to  OutputR_enab
   receive          B0
   set B0           to  "1"
end vector

vector OutputB0_high_rvrse_B0
   initialize       to  OutputR_enab_all
   receive          B0
   set B0           to  "1"
end vector

vector OutputB0_low_B0
   initialize       to  OutputR_enab
   receive          B0
   set B0           to  "0"
end vector

vector OutputB0_low_rvrse_B0
   initialize       to  OutputR_enab_all
   receive          B0
   set B0           to  "0"
end vector

vector InputB1_high_B1
   initialize       to  Keep_states_S
   drive            B1
   set B1           to  "1"
end vector

vector InputB1_high_rvrse_B1
   initialize       to  Keep_states_all
   drive            B1
   set B1           to  "1"
end vector

vector InputB1_low_B1
   initialize       to  Keep_states_S
   drive            B1
   set B1           to  "0"
end vector

vector InputB1_low_rvrse_B1
   initialize       to  Keep_states_all
   drive            B1
   set B1           to  "0"
end vector

vector OutputB1_high_B1
   initialize       to  OutputR_enab
   receive          B1
   set B1           to  "1"
end vector

vector OutputB1_high_rvrse_B1
   initialize       to  OutputR_enab_all
   receive          B1
   set B1           to  "1"
end vector

vector OutputB1_low_B1
   initialize       to  OutputR_enab
   receive          B1
   set B1           to  "0"
end vector

vector OutputB1_low_rvrse_B1
   initialize       to  OutputR_enab_all
   receive          B1
   set B1           to  "0"
end vector

vector InputB2_high_B2
   initialize       to  Keep_states_S
   drive            B2
   set B2           to  "1"
end vector

vector InputB2_high_rvrse_B2
   initialize       to  Keep_states_all
   drive            B2
   set B2           to  "1"
end vector

vector InputB2_low_B2
   initialize       to  Keep_states_S
   drive            B2
   set B2           to  "0"
end vector

vector InputB2_low_rvrse_B2
   initialize       to  Keep_states_all
   drive            B2
   set B2           to  "0"
end vector

vector OutputB2_high_B2
   initialize       to  OutputR_enab
   receive          B2
   set B2           to  "1"
end vector

vector OutputB2_high_rvrse_B2
   initialize       to  OutputR_enab_all
   receive          B2
   set B2           to  "1"
end vector

vector OutputB2_low_B2
   initialize       to  OutputR_enab
   receive          B2
   set B2           to  "0"
end vector

vector OutputB2_low_rvrse_B2
   initialize       to  OutputR_enab_all
   receive          B2
   set B2           to  "0"
end vector

vector InputB3_high_B3
   initialize       to  Keep_states_S
   drive            B3
   set B3           to  "1"
end vector

vector InputB3_high_rvrse_B3
   initialize       to  Keep_states_all
   drive            B3
   set B3           to  "1"
end vector

vector InputB3_low_B3
   initialize       to  Keep_states_S
   drive            B3
   set B3           to  "0"
end vector

vector InputB3_low_rvrse_B3
   initialize       to  Keep_states_all
   drive            B3
   set B3           to  "0"
end vector

vector OutputB3_high_B3
   initialize       to  OutputR_enab
   receive          B3
   set B3           to  "1"
end vector

vector OutputB3_high_rvrse_B3
   initialize       to  OutputR_enab_all
   receive          B3
   set B3           to  "1"
end vector

vector OutputB3_low_B3
   initialize       to  OutputR_enab
   receive          B3
   set B3           to  "0"
end vector

vector OutputB3_low_rvrse_B3
   initialize       to  OutputR_enab_all
   receive          B3
   set B3           to  "0"
end vector

vector InputB4_high_B4
   initialize       to  Keep_states_S
   drive            B4
   set B4           to  "1"
end vector

vector InputB4_high_rvrse_B4
   initialize       to  Keep_states_all
   drive            B4
   set B4           to  "1"
end vector

vector InputB4_low_B4
   initialize       to  Keep_states_S
   drive            B4
   set B4           to  "0"
end vector

vector InputB4_low_rvrse_B4
   initialize       to  Keep_states_all
   drive            B4
   set B4           to  "0"
end vector

vector OutputB4_high_B4
   initialize       to  OutputR_enab
   receive          B4
   set B4           to  "1"
end vector

vector OutputB4_high_rvrse_B4
   initialize       to  OutputR_enab_all
   receive          B4
   set B4           to  "1"
end vector

vector OutputB4_low_B4
   initialize       to  OutputR_enab
   receive          B4
   set B4           to  "0"
end vector

vector OutputB4_low_rvrse_B4
   initialize       to  OutputR_enab_all
   receive          B4
   set B4           to  "0"
end vector

vector InputB5_high_B5
   initialize       to  Keep_states_S
   drive            B5
   set B5           to  "1"
end vector

vector InputB5_high_rvrse_B5
   initialize       to  Keep_states_all
   drive            B5
   set B5           to  "1"
end vector

vector InputB5_low_B5
   initialize       to  Keep_states_S
   drive            B5
   set B5           to  "0"
end vector

vector InputB5_low_rvrse_B5
   initialize       to  Keep_states_all
   drive            B5
   set B5           to  "0"
end vector

vector OutputB5_high_B5
   initialize       to  OutputR_enab
   receive          B5
   set B5           to  "1"
end vector

vector OutputB5_high_rvrse_B5
   initialize       to  OutputR_enab_all
   receive          B5
   set B5           to  "1"
end vector

vector OutputB5_low_B5
   initialize       to  OutputR_enab
   receive          B5
   set B5           to  "0"
end vector

vector OutputB5_low_rvrse_B5
   initialize       to  OutputR_enab_all
   receive          B5
   set B5           to  "0"
end vector

vector InputB6_high_B6
   initialize       to  Keep_states_S
   drive            B6
   set B6           to  "1"
end vector

vector InputB6_high_rvrse_B6
   initialize       to  Keep_states_all
   drive            B6
   set B6           to  "1"
end vector

vector InputB6_low_B6
   initialize       to  Keep_states_S
   drive            B6
   set B6           to  "0"
end vector

vector InputB6_low_rvrse_B6
   initialize       to  Keep_states_all
   drive            B6
   set B6           to  "0"
end vector

vector OutputB6_high_B6
   initialize       to  OutputR_enab
   receive          B6
   set B6           to  "1"
end vector

vector OutputB6_high_rvrse_B6
   initialize       to  OutputR_enab_all
   receive          B6
   set B6           to  "1"
end vector

vector OutputB6_low_B6
   initialize       to  OutputR_enab
   receive          B6
   set B6           to  "0"
end vector

vector OutputB6_low_rvrse_B6
   initialize       to  OutputR_enab_all
   receive          B6
   set B6           to  "0"
end vector

vector InputB7_high_B7
   initialize       to  Keep_states_S
   drive            B7
   set B7           to  "1"
end vector

vector InputB7_high_rvrse_B7
   initialize       to  Keep_states_all
   drive            B7
   set B7           to  "1"
end vector

vector InputB7_low_B7
   initialize       to  Keep_states_S
   drive            B7
   set B7           to  "0"
end vector

vector InputB7_low_rvrse_B7
   initialize       to  Keep_states_all
   drive            B7
   set B7           to  "0"
end vector

vector OutputB7_high_B7
   initialize       to  OutputR_enab
   receive          B7
   set B7           to  "1"
end vector

vector OutputB7_high_rvrse_B7
   initialize       to  OutputR_enab_all
   receive          B7
   set B7           to  "1"
end vector

vector OutputB7_low_B7
   initialize       to  OutputR_enab
   receive          B7
   set B7           to  "0"
end vector

vector OutputB7_low_rvrse_B7
   initialize       to  OutputR_enab_all
   receive          B7
   set B7           to  "0"
end vector

!*****************************************************************************!
!************************* Vector Execution Section **************************!
!*****************************************************************************!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with R0.

unit "awaretest R0 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA0_high_A0
  execute Rreg_latch_A0
  execute Keep_states_R
  execute OutputB0_high_B0

  execute Rreg_clk_low
  execute InputA0_low_A0
  execute Rreg_latch_A0
  execute Keep_states_R
  execute OutputB0_low_B0
end unit

unit "awaretest R1 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA1_high_A1
  execute Rreg_latch_A1
  execute Keep_states_R
  execute OutputB1_high_B1

  execute Rreg_clk_low
  execute InputA1_low_A1
  execute Rreg_latch_A1
  execute Keep_states_R
  execute OutputB1_low_B1
end unit

unit "awaretest R2 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA2_high_A2
  execute Rreg_latch_A2
  execute Keep_states_R
  execute OutputB2_high_B2

  execute Rreg_clk_low
  execute InputA2_low_A2
  execute Rreg_latch_A2
  execute Keep_states_R
  execute OutputB2_low_B2
end unit

unit "awaretest R3 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA3_high_A3
  execute Rreg_latch_A3
  execute Keep_states_R
  execute OutputB3_high_B3

  execute Rreg_clk_low
  execute InputA3_low_A3
  execute Rreg_latch_A3
  execute Keep_states_R
  execute OutputB3_low_B3
end unit

unit "awaretest R4 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA4_high_A4
  execute Rreg_latch_A4
  execute Keep_states_R
  execute OutputB4_high_B4

  execute Rreg_clk_low
  execute InputA4_low_A4
  execute Rreg_latch_A4
  execute Keep_states_R
  execute OutputB4_low_B4
end unit

unit "awaretest R5 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA5_high_A5
  execute Rreg_latch_A5
  execute Keep_states_R
  execute OutputB5_high_B5

  execute Rreg_clk_low
  execute InputA5_low_A5
  execute Rreg_latch_A5
  execute Keep_states_R
  execute OutputB5_low_B5
end unit

unit "awaretest R6 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA6_high_A6
  execute Rreg_latch_A6
  execute Keep_states_R
  execute OutputB6_high_B6

  execute Rreg_clk_low
  execute InputA6_low_A6
  execute Rreg_latch_A6
  execute Keep_states_R
  execute OutputB6_low_B6
end unit

unit "awaretest R7 Test"
  execute Initial_R
  execute Rreg_enable

  execute Rreg_clk_low
  execute InputA7_high_A7
  execute Rreg_latch_A7
  execute Keep_states_R
  execute OutputB7_high_B7

  execute Rreg_clk_low
  execute InputA7_low_A7
  execute Rreg_latch_A7
  execute Keep_states_R
  execute OutputB7_low_B7
end unit

unit "Test S0"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB0_high_B0
  execute Sreg_latch_B0
  execute Keep_states_S
  execute OutputA0_high_A0

  execute Sreg_clk_low
  execute InputB0_low_B0
  execute Sreg_latch_B0
  execute Keep_states_S
  execute OutputA0_low_A0
end unit

unit "Test S1"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB1_high_B1
  execute Sreg_latch_B1
  execute Keep_states_S
  execute OutputA1_high_A1

  execute Sreg_clk_low
  execute InputB1_low_B1
  execute Sreg_latch_B1
  execute Keep_states_S
  execute OutputA1_low_A1
end unit

unit "Test S2"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB2_high_B2
  execute Sreg_latch_B2
  execute Keep_states_S
  execute OutputA2_high_A2

  execute Sreg_clk_low
  execute InputB2_low_B2
  execute Sreg_latch_B2
  execute Keep_states_S
  execute OutputA2_low_A2
end unit

unit "Test S3"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB3_high_B3
  execute Sreg_latch_B3
  execute Keep_states_S
  execute OutputA3_high_A3

  execute Sreg_clk_low
  execute InputB3_low_B3
  execute Sreg_latch_B3
  execute Keep_states_S
  execute OutputA3_low_A3
end unit

unit "Test S4"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB4_high_B4
  execute Sreg_latch_B4
  execute Keep_states_S
  execute OutputA4_high_A4

  execute Sreg_clk_low
  execute InputB4_low_B4
  execute Sreg_latch_B4
  execute Keep_states_S
  execute OutputA4_low_A4
end unit

unit "Test S5"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB5_high_B5
  execute Sreg_latch_B5
  execute Keep_states_S
  execute OutputA5_high_A5

  execute Sreg_clk_low
  execute InputB5_low_B5
  execute Sreg_latch_B5
  execute Keep_states_S
  execute OutputA5_low_A5
end unit

unit "Test S6"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB6_high_B6
  execute Sreg_latch_B6
  execute Keep_states_S
  execute OutputA6_high_A6

  execute Sreg_clk_low
  execute InputB6_low_B6
  execute Sreg_latch_B6
  execute Keep_states_S
  execute OutputA6_low_A6
end unit

unit "Test S7"
  execute Initial_S
  execute Sreg_enable

  execute Sreg_clk_low
  execute InputB7_high_B7
  execute Sreg_latch_B7
  execute Keep_states_S
  execute OutputA7_high_A7

  execute Sreg_clk_low
  execute InputB7_low_B7
  execute Sreg_latch_B7
  execute Keep_states_S
  execute OutputA7_low_A7
end unit

!*********************************************************************

unit "Test R register nothing tied"
!*****************************************************************************!
!This unit tests the R register with none of the control pins tied high or    !
!low. The bits of each register are treated as groups.                        !
!*****************************************************************************!
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputR_10101010_all
  execute Rreg_latch_all
  execute OutputR_10101010_all
  execute Rreg_clk_low_all
  execute InputR_01010101_all
  execute Rreg_latch_all
  execute OutputR_01010101_all
  execute Rreg_clk_low_all
  execute InputR_10010010_all
  execute Rreg_latch_all
  execute OutputR_10010010_all
  execute Rreg_clk_low_all
  execute InputR_00100100_all
  execute Rreg_latch_all
  execute OutputR_00100100_all
  execute Rreg_clk_low_all
  execute InputR_10001000_all
  execute Rreg_latch_all
  execute OutputR_10001000_all
  execute Rreg_clk_low_all
  execute InputR_00010001_all
  execute Rreg_latch_all
  execute OutputR_00010001_all
end unit


unit "Test S register nothing tied"
!*****************************************************************************!
!This unit tests the S register with none of the control pins tied high or    !
!low. The bits of each register are treated as groups.                        !
!*****************************************************************************!
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputS_10101010_all
  execute Sreg_latch_all
  execute OutputS_10101010_all
  execute Sreg_clk_low_all
  execute InputS_01010101_all
  execute Sreg_latch_all
  execute OutputS_01010101_all
  execute Sreg_clk_low_all
  execute InputS_10010010_all
  execute Sreg_latch_all
  execute OutputS_10010010_all
  execute Sreg_clk_low_all
  execute InputS_00100100_all
  execute Sreg_latch_all
  execute OutputS_00100100_all
  execute Sreg_clk_low_all
  execute InputS_10001000_all
  execute Sreg_latch_all
  execute OutputS_10001000_all
  execute Sreg_clk_low_all
  execute InputS_00010001_all
  execute Sreg_latch_all
  execute OutputS_00010001_all
end unit


unit "Test R0_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute OutputB0_high
  execute Rreg_clk_low
  execute InputA0_low
  execute Rreg_latch
  execute OutputB0_low
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute OutputB0_high
end unit

unit "Test R1_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_high
  execute Rreg_clk_low
  execute InputA1_low
  execute Rreg_latch
  execute OutputB1_low
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_high
end unit

unit "Test R2_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_high
  execute Rreg_clk_low
  execute InputA2_low
  execute Rreg_latch
  execute OutputB2_low
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_high
end unit

unit "Test R3_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_high
  execute Rreg_clk_low
  execute InputA3_low
  execute Rreg_latch
  execute OutputB3_low
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_high
end unit

unit "Test R4_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_high
  execute Rreg_clk_low
  execute InputA4_low
  execute Rreg_latch
  execute OutputB4_low
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_high
end unit

unit "Test R5_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_high
  execute Rreg_clk_low
  execute InputA5_low
  execute Rreg_latch
  execute OutputB5_low
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_high
end unit

unit "Test R6_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_high
  execute Rreg_clk_low
  execute InputA6_low
  execute Rreg_latch
  execute OutputB6_low
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_high
end unit

unit "Test R7_bit OEBR tied low"
  execute Initial_R_0EBR_bar_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_high
  execute Rreg_clk_low
  execute InputA7_low
  execute Rreg_latch
  execute OutputB7_low
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_high
end unit

unit "Test S0_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_high
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test S1_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB1_high
  execute Sreg_latch
  execute OutputA1_high
  execute Sreg_clk_low
  execute InputB1_low
  execute Sreg_latch
  execute OutputA1_low
  execute Sreg_clk_low
  execute InputB1_high
  execute Sreg_latch
  execute OutputA1_high
end unit

unit "Test S2_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB2_high
  execute Sreg_latch
  execute OutputA2_high
  execute Sreg_clk_low
  execute InputB2_low
  execute Sreg_latch
  execute OutputA2_low
  execute Sreg_clk_low
  execute InputB2_high
  execute Sreg_latch
  execute OutputA2_high
end unit

unit "Test S3_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB3_high
  execute Sreg_latch
  execute OutputA3_high
  execute Sreg_clk_low
  execute InputB3_low
  execute Sreg_latch
  execute OutputA3_low
  execute Sreg_clk_low
  execute InputB3_high
  execute Sreg_latch
  execute OutputA3_high
end unit

unit "Test S4_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB4_high
  execute Sreg_latch
  execute OutputA4_high
  execute Sreg_clk_low
  execute InputB4_low
  execute Sreg_latch
  execute OutputA4_low
  execute Sreg_clk_low
  execute InputB4_high
  execute Sreg_latch
  execute OutputA4_high
end unit

unit "Test S5_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB5_high
  execute Sreg_latch
  execute OutputA5_high
  execute Sreg_clk_low
  execute InputB5_low
  execute Sreg_latch
  execute OutputA5_low
  execute Sreg_clk_low
  execute InputB5_high
  execute Sreg_latch
  execute OutputA5_high
end unit

unit "Test S6_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB6_high
  execute Sreg_latch
  execute OutputA6_high
  execute Sreg_clk_low
  execute InputB6_low
  execute Sreg_latch
  execute OutputA6_low
  execute Sreg_clk_low
  execute InputB6_high
  execute Sreg_latch
  execute OutputA6_high
end unit

unit "Test S7_bit OEAS tied low"
  execute Initial_S_0EAS_bar_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB7_high
  execute Sreg_latch
  execute OutputA7_high
  execute Sreg_clk_low
  execute InputB7_low
  execute Sreg_latch
  execute OutputA7_low
  execute Sreg_clk_low
  execute InputB7_high
  execute Sreg_latch
  execute OutputA7_high
end unit


unit "Test R0_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute OutputB0_high
  execute Rreg_clk_low
  execute InputA0_low
  execute Rreg_latch
  execute OutputB0_low
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute OutputB0_high
end unit

unit "Test R1_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_high
  execute Rreg_clk_low
  execute InputA1_low
  execute Rreg_latch
  execute OutputB1_low
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_high
end unit

unit "Test R2_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_high
  execute Rreg_clk_low
  execute InputA2_low
  execute Rreg_latch
  execute OutputB2_low
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_high
end unit

unit "Test R3_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_high
  execute Rreg_clk_low
  execute InputA3_low
  execute Rreg_latch
  execute OutputB3_low
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_high
end unit

unit "Test R4_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_high
  execute Rreg_clk_low
  execute InputA4_low
  execute Rreg_latch
  execute OutputB4_low
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_high
end unit

unit "Test R5_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_high
  execute Rreg_clk_low
  execute InputA5_low
  execute Rreg_latch
  execute OutputB5_low
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_high
end unit

unit "Test R6_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_high
  execute Rreg_clk_low
  execute InputA6_low
  execute Rreg_latch
  execute OutputB6_low
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_high
end unit

unit "Test R7_bit CER tied low"
  execute Initial_R_CER_bar_low
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_high
  execute Rreg_clk_low
  execute InputA7_low
  execute Rreg_latch
  execute OutputB7_low
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_high
end unit

unit "Test S0_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_high
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test S1_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB1_high
  execute Sreg_latch
  execute OutputA1_high
  execute Sreg_clk_low
  execute InputB1_low
  execute Sreg_latch
  execute OutputA1_low
  execute Sreg_clk_low
  execute InputB1_high
  execute Sreg_latch
  execute OutputA1_high
end unit

unit "Test S2_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB2_high
  execute Sreg_latch
  execute OutputA2_high
  execute Sreg_clk_low
  execute InputB2_low
  execute Sreg_latch
  execute OutputA2_low
  execute Sreg_clk_low
  execute InputB2_high
  execute Sreg_latch
  execute OutputA2_high
end unit

unit "Test S3_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB3_high
  execute Sreg_latch
  execute OutputA3_high
  execute Sreg_clk_low
  execute InputB3_low
  execute Sreg_latch
  execute OutputA3_low
  execute Sreg_clk_low
  execute InputB3_high
  execute Sreg_latch
  execute OutputA3_high
end unit

unit "Test S4_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB4_high
  execute Sreg_latch
  execute OutputA4_high
  execute Sreg_clk_low
  execute InputB4_low
  execute Sreg_latch
  execute OutputA4_low
  execute Sreg_clk_low
  execute InputB4_high
  execute Sreg_latch
  execute OutputA4_high
end unit

unit "Test S5_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB5_high
  execute Sreg_latch
  execute OutputA5_high
  execute Sreg_clk_low
  execute InputB5_low
  execute Sreg_latch
  execute OutputA5_low
  execute Sreg_clk_low
  execute InputB5_high
  execute Sreg_latch
  execute OutputA5_high
end unit

unit "Test S6_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB6_high
  execute Sreg_latch
  execute OutputA6_high
  execute Sreg_clk_low
  execute InputB6_low
  execute Sreg_latch
  execute OutputA6_low
  execute Sreg_clk_low
  execute InputB6_high
  execute Sreg_latch
  execute OutputA6_high
end unit

unit "Test S7_bit CES tied low"
  execute Initial_S_CES_bar_low
  execute Sreg_clk_low
  execute InputB7_high
  execute Sreg_latch
  execute OutputA7_high
  execute Sreg_clk_low
  execute InputB7_low
  execute Sreg_latch
  execute OutputA7_low
  execute Sreg_clk_low
  execute InputB7_high
  execute Sreg_latch
  execute OutputA7_high
end unit

!******************************************************************************!
!This unit tests the R register much like the first unit but CPS and CES_bar   !
!are ignored.                                                                  !
!******************************************************************************!
unit "Test R register-ignore S controls"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputR_10101010
  execute Rreg_latch
  execute OutputR_10101010
  execute Rreg_clk_low
  execute InputR_01010101
  execute Rreg_latch
  execute OutputR_01010101
  execute Rreg_clk_low
  execute InputR_10010010
  execute Rreg_latch
  execute OutputR_10010010
  execute Rreg_clk_low
  execute InputR_00100100
  execute Rreg_latch
  execute OutputR_00100100
  execute Rreg_clk_low
  execute InputR_10001000
  execute Rreg_latch
  execute OutputR_10001000
  execute Rreg_clk_low
  execute InputR_00010001
  execute Rreg_latch
  execute OutputR_00010001
end unit


!******************************************************************************!
!This unit tests the S register much like the second unit but CPR and CER_bar
!are ignored.
!******************************************************************************!

unit "Test S register-ignore R controls"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputS_10101010
  execute Sreg_latch
  execute OutputS_10101010
  execute Sreg_clk_low
  execute InputS_01010101
  execute Sreg_latch
  execute OutputS_01010101
  execute Sreg_clk_low
  execute InputS_10010010
  execute Sreg_latch
  execute OutputS_10010010
  execute Sreg_clk_low
  execute InputS_00100100
  execute Sreg_latch
  execute OutputS_00100100
  execute Sreg_clk_low
  execute InputS_10001000
  execute Sreg_latch
  execute OutputS_10001000
  execute Sreg_clk_low
  execute InputS_00010001
  execute Sreg_latch
  execute OutputS_00010001
end unit

!******************************************************************************!
!The following "reversing" units latch data into the first register then using !
!the first register's output lines, the data is latched into the second        !
!register.                                                                     !
!******************************************************************************!
unit "Test data reversing from A0"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA0_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA0_high_rvrse
  execute Rreg_latch_all
  execute OutputA0_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA0_low_rvrse
  execute Rreg_latch_all
  execute OutputA0_high_rvrse
end unit

unit "Test data reversing from A1"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA1_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA1_high_rvrse
  execute Rreg_latch_all
  execute OutputA1_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA1_low_rvrse
  execute Rreg_latch_all
  execute OutputA1_high_rvrse
end unit

unit "Test data reversing from A2"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA2_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA2_high_rvrse
  execute Rreg_latch_all
  execute OutputA2_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA2_low_rvrse
  execute Rreg_latch_all
  execute OutputA2_high_rvrse
end unit

unit "Test data reversing from A3"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA3_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA3_high_rvrse
  execute Rreg_latch_all
  execute OutputA3_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA3_low_rvrse
  execute Rreg_latch_all
  execute OutputA3_high_rvrse
end unit

unit "Test data reversing from A4"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA4_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA4_high_rvrse
  execute Rreg_latch_all
  execute OutputA4_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA4_low_rvrse
  execute Rreg_latch_all
  execute OutputA4_high_rvrse
end unit

unit "Test data reversing from A5"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA5_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA5_high_rvrse
  execute Rreg_latch_all
  execute OutputA5_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA5_low_rvrse
  execute Rreg_latch_all
  execute OutputA5_high_rvrse
end unit

unit "Test data reversing from A6"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA6_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA6_high_rvrse
  execute Rreg_latch_all
  execute OutputA6_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA6_low_rvrse
  execute Rreg_latch_all
  execute OutputA6_high_rvrse
end unit

unit "Test data reversing from A7"
  execute Initial_all
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute InputA7_low_rvrse
  execute Rreg_latch_all
  execute RegisterR_output_enable
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute RegisterR_output_disabled
  execute Rreg_clk_low_all
  execute InputA7_high_rvrse
  execute Rreg_latch_all
  execute OutputA7_low_rvrse
  execute RegisterS_output_disabled
  execute RegisterR_output_enable
  execute Sreg_clk_low_all
  execute Clock_latch_S
  execute Rreg_clk_low_all
  execute InputA7_low_rvrse
  execute Rreg_latch_all
  execute OutputA7_high_rvrse
end unit

unit "Test data reversing from B0"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB0_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB0_high_rvrse
  execute Sreg_latch_all
  execute OutputB0_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB0_low_rvrse
  execute Sreg_latch_all
  execute OutputB0_high_rvrse
end unit

unit "Test data reversing from B1"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB1_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB1_high_rvrse
  execute Sreg_latch_all
  execute OutputB1_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB1_low_rvrse
  execute Sreg_latch_all
  execute OutputB1_high_rvrse
end unit

unit "Test data reversing from B2"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB2_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB2_high_rvrse
  execute Sreg_latch_all
  execute OutputB2_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB2_low_rvrse
  execute Sreg_latch_all
  execute OutputB2_high_rvrse
end unit

unit "Test data reversing from B3"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB3_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB3_high_rvrse
  execute Sreg_latch_all
  execute OutputB3_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB3_low_rvrse
  execute Sreg_latch_all
  execute OutputB3_high_rvrse
end unit

unit "Test data reversing from B4"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB4_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB4_high_rvrse
  execute Sreg_latch_all
  execute OutputB4_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB4_low_rvrse
  execute Sreg_latch_all
  execute OutputB4_high_rvrse
end unit

unit "Test data reversing from B5"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB5_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB5_high_rvrse
  execute Sreg_latch_all
  execute OutputB5_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB5_low_rvrse
  execute Sreg_latch_all
  execute OutputB5_high_rvrse
end unit

unit "Test data reversing from B6"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB6_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB6_high_rvrse
  execute Sreg_latch_all
  execute OutputB6_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB6_low_rvrse
  execute Sreg_latch_all
  execute OutputB6_high_rvrse
end unit

unit "Test data reversing from B7"
  execute Initial_all
  execute Sreg_enable_all
  execute Sreg_clk_low_all
  execute InputB7_low_rvrse
  execute Sreg_latch_all
  execute RegisterS_output_enable
  execute Rreg_enable_all
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute RegisterS_output_disabled
  execute Sreg_clk_low_all
  execute InputB7_high_rvrse
  execute Sreg_latch_all
  execute OutputB7_low_rvrse
  execute RegisterR_output_disabled
  execute RegisterS_output_enable
  execute Rreg_clk_low_all
  execute Clock_latch_R
  execute Sreg_clk_low_all
  execute InputB7_low_rvrse
  execute Sreg_latch_all
  execute OutputB7_high_rvrse
end unit

unit "Test R0"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute Keep_states_R
  execute OutputB0_high
  execute Rreg_clk_low
  execute InputA0_low
  execute Rreg_latch
  execute Keep_states_R
  execute OutputB0_low
end unit

unit "Test R1"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_high
  execute Rreg_clk_low
  execute InputA1_low
  execute Rreg_latch
  execute OutputB1_low
end unit

unit "Test R2"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_high
  execute Rreg_clk_low
  execute InputA2_low
  execute Rreg_latch
  execute OutputB2_low
end unit

unit "Test R3"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_high
  execute Rreg_clk_low
  execute InputA3_low
  execute Rreg_latch
  execute OutputB3_low
end unit

unit "Test R4"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_high
  execute Rreg_clk_low
  execute InputA4_low
  execute Rreg_latch
  execute OutputB4_low
end unit

unit "Test R5"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_high
  execute Rreg_clk_low
  execute InputA5_low
  execute Rreg_latch
  execute OutputB5_low
end unit

unit "Test R6"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_high
  execute Rreg_clk_low
  execute InputA6_low
  execute Rreg_latch
  execute OutputB6_low
end unit

unit "Test R7"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_high
  execute Rreg_clk_low
  execute InputA7_low
  execute Rreg_latch
  execute OutputB7_low
end unit

unit "Test S0"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA0_high
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA0_low
end unit

unit "Test S1"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB1_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA1_high
  execute Sreg_clk_low
  execute InputB1_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA1_low
end unit

unit "Test S2"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB2_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA2_high
  execute Sreg_clk_low
  execute InputB2_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA2_low
end unit

unit "Test S3"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB3_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA3_high
  execute Sreg_clk_low
  execute InputB3_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA3_low
end unit

unit "Test S4"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB4_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA4_high
  execute Sreg_clk_low
  execute InputB4_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA4_low
end unit

unit "Test S5"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB5_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA5_high
  execute Sreg_clk_low
  execute InputB5_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA5_low
end unit

unit "Test S6"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB6_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA6_high
  execute Sreg_clk_low
  execute InputB6_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA6_low
end unit

unit "Test S7"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB7_high
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA7_high
  execute Sreg_clk_low
  execute InputB7_low
  execute Sreg_latch
  execute Keep_states_S
  execute OutputA7_low
end unit

!******************************************************************************!
!Each register's clock enable is tested at each bit in the register.           !
!******************************************************************************!
unit "Test bit R0 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA0_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute OutputB0_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA0_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA0_low
  execute Rreg_latch
  execute OutputB0_high
end unit

unit "Test bit R1 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA1_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute OutputB1_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA1_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA1_low
  execute Rreg_latch
  execute OutputB1_high
end unit

unit "Test bit R2 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA2_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute OutputB2_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA2_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA2_low
  execute Rreg_latch
  execute OutputB2_high
end unit

unit "Test bit R3 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA3_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute OutputB3_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA3_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA3_low
  execute Rreg_latch
  execute OutputB3_high
end unit

unit "Test bit R4 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA4_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute OutputB4_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA4_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA4_low
  execute Rreg_latch
  execute OutputB4_high
end unit

unit "Test bit R5 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA5_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute OutputB5_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA5_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA5_low
  execute Rreg_latch
  execute OutputB5_high
end unit

unit "Test bit R6 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA6_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute OutputB6_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA6_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA6_low
  execute Rreg_latch
  execute OutputB6_high
end unit

unit "Test bit R7 clock disable"
  execute Initial_R
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA7_low
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute OutputB7_low
  execute Rreg_enable
  execute Rreg_clk_low
  execute InputA7_high
  execute Rreg_latch
  execute Rreg_clk_disable
  execute Rreg_clk_low
  execute InputA7_low
  execute Rreg_latch
  execute OutputB7_high
end unit

unit "Test bit S0 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S1 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S2 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S3 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S4 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S5 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S6 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit

unit "Test bit S7 clock disable"
  execute Initial_S
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute OutputA0_low
  execute Sreg_enable
  execute Sreg_clk_low
  execute InputB0_high
  execute Sreg_latch
  execute Sreg_clk_disable
  execute Sreg_clk_low
  execute InputB0_low
  execute Sreg_latch
  execute OutputA0_high
end unit