!!!!    6    0    1  991755366  V7591                                         

! Device           : 74ls672
! Function         : 4-bit Universial Shift Register/Latch
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

! Note:  This device has outputs that can be set to high impedance. Inorder
!        to test Gbar (pin 12) pullups are needed on Qd_Qa (pins 15-18).

vector cycle  500n
receive delay 400n

! warning "Pull-ups are required to test high-impedance outputs."

assign   VCC         to pins  20
assign   GND         to pins  10

assign   D_A         to pins  6,5,4,3
assign   D_A0        to pins  3         !AT Added for minimum pin test.
assign   D_A1        to pins  4         !AT Added for minimum pin test.
assign   D_A2        to pins  5         !AT Added for minimum pin test.
assign   D_A3        to pins  6         !AT Added for minimum pin test.

assign   SL_SER      to pins  7
assign   SR_SER      to pins  1
assign   SCK         to pins  2
assign   S1_S0       to pins  13,14
assign   SCLRbar     to pins  8
assign   RCK         to pins  9
assign   R_Sbar      to pins  11
assign   Gbar        to pins  12

assign   Qd_Qa       to pins  15,16,17,18
assign   Qd_Qa0      to pins  18           !AT Added for minimum pin test.
assign   Qd_Qa1      to pins  17           !AT Added for minimum pin test.
assign   Qd_Qa2      to pins  16           !AT Added for minimum pin test.
assign   Qd_Qa3      to pins  15           !AT Added for minimum pin test.

assign   CASC        to pins  19

family    TTL

power          VCC,GND

inputs         D_A, SL_SER, SR_SER, SCK, S1_S0
inputs         SCLRbar, RCK, R_Sbar, Gbar
inputs         D_A0, D_A1, D_A2, D_A3      !AT Added for minimum pin test.

outputs        Qd_Qa, CASC
outputs        Qd_Qa0, Qd_Qa1, Qd_Qa2, Qd_Qa3  !AT Added for minimum pin test.

disable        Qd_Qa    with  Gbar to "1"

when Gbar is "1" inactive Qd_Qa

trace Qd_QA, CASC to D_A, SL_SER, SR_SER, SCK, S1_S0
trace Qd_Qa, CASC to SCLRbar, RCK, R_Sbar, Gbar

set load on groups  Qd_Qa to pull up

!***************************************************************
!***************************************************************

vector   Setup
         set   D_A      to "0000"
         set   Gbar     to "0"
         set   RCK      to "0"
         set   R_Sbar   to "0"
         set   SCK      to "0"
         set   SCLRbar  to "1"
         set   SL_SER   to "0"
         set   SR_SER   to "0"
         set   S1_S0    to "kk"
end vector

vector   Keep_Control
         set   D_A      to "kkkk"
         set   Gbar     to "k"
         set   RCK      to "k"
         set   R_Sbar   to "k"
         set   SCK      to "k"
         set   SCLRbar  to "k"
         set   SL_SER   to "k"
         set   SR_SER   to "k"
         set   S1_S0    to "kk"
end vector

vector   CASC_high
         initialize to Keep_Control
         set   CASC     to "1"
end vector

vector   CASC_low
         initialize to Keep_Control
         set   CASC     to "0"
end vector

vector   Clock_Latch
         initialize to Keep_Control
         set   RCK      to "t"
end vector

vector   Clock_Shift_Register
         initialize to Keep_Control
         set   SCK      to "t"
end vector

vector   D_A_0101
         initialize to Keep_Control
         set   D_A      to "0101"
end vector

vector   D_A_1010
         initialize to Keep_Control
         set   D_A      to "1010"
end vector

vector   Disable
         initialize to Keep_Control
         set   Gbar     to "1"
end vector

vector   Disable_test_using_pullups
         initialize to Keep_Control
         set   Qd_Qa    to "1111"
end vector

vector   Parallel_Load_mode
         set   S1_S0    to "11"
end vector

vector   Qd_Qa_0000
         initialize to Keep_Control
         set   Qd_Qa    to "0000"
end vector

vector   Qd_Qa_0101
         initialize to Keep_Control
         set   Qd_Qa    to "0101"
end vector

vector   Qd_Qa_1010
         initialize to Keep_Control
         set   Qd_Qa    to "1010"
end vector

vector   R_Sbar_high
         initialize to Keep_Control
         set   R_Sbar   to "1"
end vector

vector   SCLRbar_low
         initialize to Keep_Control
         set   SCLRbar  to "0"
end vector

vector   Shift_Left_mode
         set   S1_S0    to "10"
end vector

vector   Shift_Right_mode
         set   S1_S0    to "01"
end vector

vector   SL_SER_high
         initialize to Keep_Control
         set   SL_SER   to "1"
end vector

vector   SL_SER_low
         initialize to Keep_Control
         set   SL_SER   to "0"
end vector

vector   SR_SER_high
         initialize to Keep_Control
         set   SR_SER   to "1"
end vector

vector   SR_SER_low
         initialize to Keep_Control
         set   SR_SER   to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   D_A_0000
         initialize to Keep_Control
         set   D_A      to "0000"
end vector

vector   D_A_1111
         initialize to Keep_Control
         set   D_A      to "1111"
end vector

vector   Qd_Qa0_0
         initialize to Keep_Control
         set   Qd_Qa0   to "0"
end vector

vector   Qd_Qa0_1
         initialize to Keep_Control
         set   Qd_Qa0   to "1"
end vector

vector   Qd_Qa1_0
         initialize to Keep_Control
         set   Qd_Qa1   to "0"
end vector

vector   Qd_Qa1_1
         initialize to Keep_Control
         set   Qd_Qa1   to "1"
end vector

vector   Qd_Qa2_0
         initialize to Keep_Control
         set   Qd_Qa2   to "0"
end vector

vector   Qd_Qa2_1
         initialize to Keep_Control
         set   Qd_Qa2   to "1"
end vector

vector   Qd_Qa3_0
         initialize to Keep_Control
         set   Qd_Qa3   to "0"
end vector

vector   Qd_Qa3_1
         initialize to Keep_Control
         set   Qd_Qa3   to "1"
end vector

!***************************************************************
!***************************************************************


!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with Qd_Qa0.

unit "awaretest Qd_Qa0 shift right Test"
   execute Shift_Right_mode
   execute Setup
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_0

   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_1
end   unit

unit "awaretest Qd_Qa1 shift right Test"
   execute Shift_Right_mode
   execute Setup
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_0

   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_1
end   unit

unit "awaretest Qd_Qa2 shift right Test"
   execute Shift_Right_mode
   execute Setup
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_0

   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_1
end   unit

unit "awaretest Qd_Qa3 shift right Test"
   execute Shift_Right_mode
   execute Setup
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_0

   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_1
end   unit

unit "awaretest Qd_Qa0 shift left Test"
   execute Shift_Left_mode
   execute Setup
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_0

   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_1
end   unit

unit "awaretest Qd_Qa1 shift left Test"
   execute Shift_Left_mode
   execute Setup
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_0

   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_1
end   unit

unit "awaretest Qd_Qa2 shift left Test"
   execute Shift_Left_mode
   execute Setup
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_0

   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_1
end   unit

unit "awaretest Qd_Qa3 shift left Test"
   execute Shift_Left_mode
   execute Setup
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_0

   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_1
end   unit

unit "awaretest Qd_Qa0 parallel load Test"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0000
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_0

   execute D_A_1111
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa0_1
end unit

unit "awaretest Qd_Qa1 parallel load Test"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0000
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_0

   execute D_A_1111
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa1_1
end unit

unit "awaretest Qd_Qa2 parallel load Test"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0000
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_0

   execute D_A_1111
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa2_1
end unit

unit "awaretest Qd_Qa3 parallel load Test"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0000
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_0

   execute D_A_1111
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa3_1
end unit


unit  "unit1 test shift right"
   execute Shift_Right_mode
   execute Setup
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101
   execute CASC_low

   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute CASC_high
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SR_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SR_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_1010
end   unit

unit  "unit2 test shift left"
   execute Shift_Left_mode
   execute Setup
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_1010
   execute CASC_low

   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute SL_SER_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101
   execute CASC_high
end   unit

unit "unit3 test parrellel load"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0101
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101

   execute D_A_1010
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_1010
end unit

unit "unit4 test latches and clear using parrellel load"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0101
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101
      execute Clock_Latch
      execute Clock_Latch
   execute R_Sbar_high
   execute SCLRbar_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101
      execute Clock_Latch
      execute Clock_Latch
   execute Qd_Qa_0000
end unit

unit "unit5 test enable with parrellel load"
   execute Parallel_Load_mode
   execute Setup
   execute D_A_0101
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Qd_Qa_0101
   execute Disable
   execute Disable_test_using_pullups
end unit

!End of test