!!!!    6    0    1  990466065  Vc800                                         

! Device           : dm85s68
! Function         : 16 x 4 Edge Triggered Registers
! revision         : B.01.00
! safeguard        : standard_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!warning  " This device has outputs that can be set in the high   "
!warning  "   impedance state.  In order to test Output Disable   "
!warning  "   (pin 12) pullups are needed on Data Outputs.        "

sequential

! safeguard    standard_ttl

vector cycle  500n
receive delay 400n

! TTL
assign   VCC         to pins 18
assign   GND         to pins 9

! Inputs

assign   Data_Inputs          to pins 16,17,1,2
assign   D0_I                 to pins 2         !AT Added for minimum pin test.
assign   D1_I                 to pins 1         !AT Added for minimum pin test.
assign   D2_I                 to pins 17        !AT Added for minimum pin test.
assign   D3_I                 to pins 16        !AT Added for minimum pin test.

assign   Address              to pins 5,4,6,3
assign   Write_Enable_bar     to pins 15

assign   Clock                to pins 14
assign   Output_Store_bar     to pins 13
assign   Output_Disable       to pins 12

! Outputs

assign   Data_Outputs         to pins 11,10,8,7
assign   D0_O                 to pins 7         !AT Added for minimum pin test.
assign   D1_O                 to pins 8         !AT Added for minimum pin test.
assign   D2_O                 to pins 10        !AT Added for minimum pin test.
assign   D3_O                 to pins 11        !AT Added for minimum pin test.

family   TTL

! TTL
power    VCC,GND

inputs    Data_Inputs,Address,Write_Enable_bar
inputs    Clock,Output_Store_bar,Output_Disable
inputs    D0_I, D1_I, D2_I, D3_I  !AT Added for minimum pin test.

outputs   Data_Outputs
outputs   D0_O, D1_O, D2_O, D3_O  !AT Added for minimum pin test.

when Output_disable is "1" inactive Data_outputs

! NOTE: the default trace specification is used

disable   Data_Outputs   with  Output_Disable  to  "1"


set load on groups  Data_Outputs  to pull up

!***************************************************************
!***************************************************************

vector  Initialize_Inputs
   set   Data_Inputs          to "0000"
   set   Address              to "0000"
   set   Write_Enable_bar     to "1"

   set   Clock                to "0"
   set   Output_Store_bar     to "1"
   set   Output_Disable       to "0"
end vector

vector  Keep_Inputs
   set   Data_Inputs          to "kkkk"
   set   Address              to "kkkk"
   set   Write_Enable_bar     to "k"

   set   Clock                to "k"
   set   Output_Store_bar     to "k"
   set   Output_Disable       to "k"
end vector

! Inputs

vector Data_Inputs_0000
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0000"
end vector

vector Data_Inputs_0001
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0001"
end vector

vector Data_Inputs_0010
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0010"
end vector

vector Data_Inputs_0011
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0011"
end vector

vector Data_Inputs_0100
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0100"
end vector

vector Data_Inputs_0101
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0101"
end vector

vector Data_Inputs_0110
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0110"
end vector

vector Data_Inputs_0111
   initialize  to Keep_Inputs
   set   Data_Inputs          to "0111"
end vector

vector Data_Inputs_1000
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1000"
end vector

vector Data_Inputs_1001
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1001"
end vector

vector Data_Inputs_1010
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1010"
end vector

vector Data_Inputs_1011
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1011"
end vector

vector Data_Inputs_1100
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1100"
end vector

vector Data_Inputs_1101
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1101"
end vector

vector Data_Inputs_1110
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1110"
end vector

vector Data_Inputs_1111
   initialize  to Keep_Inputs
   set   Data_Inputs          to "1111"
end vector

vector Address_0000
   initialize  to Keep_Inputs
   set   Address              to "0000"
end vector

vector Address_0001
   initialize  to Keep_Inputs
   set   Address              to "0001"
end vector

vector Address_0010
   initialize  to Keep_Inputs
   set   Address              to "0010"
end vector

vector Address_0011
   initialize  to Keep_Inputs
   set   Address              to "0011"
end vector

vector Address_0100
   initialize  to Keep_Inputs
   set   Address              to "0100"
end vector

vector Address_0101
   initialize  to Keep_Inputs
   set   Address              to "0101"
end vector

vector Address_0110
   initialize  to Keep_Inputs
   set   Address              to "0110"
end vector

vector Address_0111
   initialize  to Keep_Inputs
   set   Address              to "0111"
end vector

vector Address_1000
   initialize  to Keep_Inputs
   set   Address              to "1000"
end vector

vector Address_1001
   initialize  to Keep_Inputs
   set   Address              to "1001"
end vector

vector Address_1010
   initialize  to Keep_Inputs
   set   Address              to "1010"
end vector

vector Address_1011
   initialize  to Keep_Inputs
   set   Address              to "1011"
end vector

vector Address_1100
   initialize  to Keep_Inputs
   set   Address              to "1100"
end vector

vector Address_1101
   initialize  to Keep_Inputs
   set   Address              to "1101"
end vector

vector Address_1110
   initialize  to Keep_Inputs
   set   Address              to "1110"
end vector

vector Address_1111
   initialize  to Keep_Inputs
   set   Address              to "1111"
end vector

vector Write_Enable_true
   initialize  to Keep_Inputs
   set   Write_Enable_bar     to "0"
end vector

vector Write_Enable_false
   initialize  to Keep_Inputs
   set   Clock                to "0"
   set   Write_Enable_bar     to "1"
end vector

vector Clock_1
   initialize  to Keep_Inputs
   set   Clock                to "1"
end vector

vector Clock_0
   initialize  to Keep_Inputs
   set   Clock                to "0"
end vector

vector Output_Store_true
   initialize  to Keep_Inputs
   set   Output_Store_bar     to "1"
end vector

vector Output_Store_false
   initialize  to Keep_Inputs
   set   Output_Store_bar     to "0"
end vector

vector Output_Disable_true
   initialize  to Keep_Inputs
   set   Output_Disable       to "1"
end vector

vector Output_Disable_false
   initialize  to Keep_Inputs
   set   Output_Disable       to "0"
end vector

! Outputs

vector Data_Outputs_0000
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0000"
end vector

vector Data_Outputs_0001
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0001"
end vector

vector Data_Outputs_0010
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0010"
end vector

vector Data_Outputs_0011
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0011"
end vector

vector Data_Outputs_0100
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0100"
end vector

vector Data_Outputs_0101
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0101"
end vector

vector Data_Outputs_0110
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0110"
end vector

vector Data_Outputs_0111
   initialize  to Keep_Inputs
   set   Data_Outputs          to "0111"
end vector

vector Data_Outputs_1000
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1000"
end vector

vector Data_Outputs_1001
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1001"
end vector

vector Data_Outputs_1010
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1010"
end vector

vector Data_Outputs_1011
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1011"
end vector

vector Data_Outputs_1100
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1100"
end vector

vector Data_Outputs_1101
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1101"
end vector

vector Data_Outputs_1110
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1110"
end vector

vector Data_Outputs_1111
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1111"
end vector

vector Data_Outputs_HIZ
   initialize  to Keep_Inputs
   set   Data_Outputs          to "1111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  Initialize_Inputs_D0
   set   D0_I                 to "0"
   set   Address              to "0000"
   set   Write_Enable_bar     to "1"

   set   Clock                to "0"
   set   Output_Store_bar     to "1"
   set   Output_Disable       to "0"
end vector

vector  Keep_Inputs_D0
   set   D0_I                 to "k"
   set   Address              to "kkkk"
   set   Write_Enable_bar     to "k"

   set   Clock                to "k"
   set   Output_Store_bar     to "k"
   set   Output_Disable       to "k"
end vector

! Inputs

vector D0_I_0
   initialize  to Keep_Inputs_D0
   set   D0_I                 to "0"
end vector

vector D0_I_1
   initialize  to Keep_Inputs_D0
   set   D0_I                 to "1"
end vector

vector Address_0000_D0
   initialize  to Keep_Inputs_D0
   set   Address              to "0000"
end vector

vector WE_t_D0
   initialize  to Keep_Inputs_D0
   set   Write_Enable_bar     to "0"
end vector

vector WE_f_D0
   initialize  to Keep_Inputs_D0
   set   Clock                to "0"
   set   Write_Enable_bar     to "1"
end vector

vector Clk1_D0
   initialize  to Keep_Inputs_D0
   set   Clock                to "1"
end vector

vector OS_t_D0
   initialize  to Keep_Inputs_D0
   set   Output_Store_bar     to "1"
end vector

vector OS_f_D0
   initialize  to Keep_Inputs_D0
   set   Output_Store_bar     to "0"
end vector

vector D0_O_0
   initialize  to Keep_Inputs_D0
   set   D0_O                  to "0"
end vector

vector D0_O_1
   initialize  to Keep_Inputs_D0
   set   D0_O                  to "1"
end vector

vector  Initialize_Inputs_D1
   set   D1_I                 to "0"
   set   Address              to "0000"
   set   Write_Enable_bar     to "1"

   set   Clock                to "0"
   set   Output_Store_bar     to "1"
   set   Output_Disable       to "0"
end vector

vector  Keep_Inputs_D1
   set   D1_I                 to "k"
   set   Address              to "kkkk"
   set   Write_Enable_bar     to "k"

   set   Clock                to "k"
   set   Output_Store_bar     to "k"
   set   Output_Disable       to "k"
end vector

! Inputs

vector D1_I_0
   initialize  to Keep_Inputs_D1
   set   D1_I                 to "0"
end vector

vector D1_I_1
   initialize  to Keep_Inputs_D1
   set   D1_I                 to "1"
end vector

vector Address_0000_D1
   initialize  to Keep_Inputs_D1
   set   Address              to "0000"
end vector

vector WE_t_D1
   initialize  to Keep_Inputs_D1
   set   Write_Enable_bar     to "0"
end vector

vector WE_f_D1
   initialize  to Keep_Inputs_D1
   set   Clock                to "0"
   set   Write_Enable_bar     to "1"
end vector

vector Clk1_D1
   initialize  to Keep_Inputs_D1
   set   Clock                to "1"
end vector

vector OS_t_D1
   initialize  to Keep_Inputs_D1
   set   Output_Store_bar     to "1"
end vector

vector OS_f_D1
   initialize  to Keep_Inputs_D1
   set   Output_Store_bar     to "0"
end vector

vector D1_O_0
   initialize  to Keep_Inputs_D1
   set   D1_O                  to "0"
end vector

vector D1_O_1
   initialize  to Keep_Inputs_D1
   set   D1_O                  to "1"
end vector

vector  Initialize_Inputs_D2
   set   D2_I                 to "0"
   set   Address              to "0000"
   set   Write_Enable_bar     to "1"

   set   Clock                to "0"
   set   Output_Store_bar     to "1"
   set   Output_Disable       to "0"
end vector

vector  Keep_Inputs_D2
   set   D2_I                 to "k"
   set   Address              to "kkkk"
   set   Write_Enable_bar     to "k"

   set   Clock                to "k"
   set   Output_Store_bar     to "k"
   set   Output_Disable       to "k"
end vector

! Inputs

vector D2_I_0
   initialize  to Keep_Inputs_D2
   set   D2_I                 to "0"
end vector

vector D2_I_1
   initialize  to Keep_Inputs_D2
   set   D2_I                 to "1"
end vector

vector Address_0000_D2
   initialize  to Keep_Inputs_D2
   set   Address              to "0000"
end vector

vector WE_t_D2
   initialize  to Keep_Inputs_D2
   set   Write_Enable_bar     to "0"
end vector

vector WE_f_D2
   initialize  to Keep_Inputs_D2
   set   Clock                to "0"
   set   Write_Enable_bar     to "1"
end vector

vector Clk1_D2
   initialize  to Keep_Inputs_D2
   set   Clock                to "1"
end vector

vector OS_t_D2
   initialize  to Keep_Inputs_D2
   set   Output_Store_bar     to "1"
end vector

vector OS_f_D2
   initialize  to Keep_Inputs_D2
   set   Output_Store_bar     to "0"
end vector

vector D2_O_0
   initialize  to Keep_Inputs_D2
   set   D2_O                  to "0"
end vector

vector D2_O_1
   initialize  to Keep_Inputs_D2
   set   D2_O                  to "1"
end vector

vector  Initialize_Inputs_D3
   set   D3_I                 to "0"
   set   Address              to "0000"
   set   Write_Enable_bar     to "1"

   set   Clock                to "0"
   set   Output_Store_bar     to "1"
   set   Output_Disable       to "0"
end vector

vector  Keep_Inputs_D3
   set   D3_I                 to "k"
   set   Address              to "kkkk"
   set   Write_Enable_bar     to "k"

   set   Clock                to "k"
   set   Output_Store_bar     to "k"
   set   Output_Disable       to "k"
end vector

! Inputs

vector D3_I_0
   initialize  to Keep_Inputs_D3
   set   D3_I                 to "0"
end vector

vector D3_I_1
   initialize  to Keep_Inputs_D3
   set   D3_I                 to "1"
end vector

vector Address_0000_D3
   initialize  to Keep_Inputs_D3
   set   Address              to "0000"
end vector

vector WE_t_D3
   initialize  to Keep_Inputs_D3
   set   Write_Enable_bar     to "0"
end vector

vector WE_f_D3
   initialize  to Keep_Inputs_D3
   set   Clock                to "0"
   set   Write_Enable_bar     to "1"
end vector

vector Clk1_D3
   initialize  to Keep_Inputs_D3
   set   Clock                to "1"
end vector

vector OS_t_D3
   initialize  to Keep_Inputs_D3
   set   Output_Store_bar     to "1"
end vector

vector OS_f_D3
   initialize  to Keep_Inputs_D3
   set   Output_Store_bar     to "0"
end vector

vector D3_O_0
   initialize  to Keep_Inputs_D3
   set   D3_O                  to "0"
end vector

vector D3_O_1
   initialize  to Keep_Inputs_D3
   set   D3_O                  to "1"
end vector

!***************************************************************
!***************************************************************

sub   Write (Address,Data)
   execute  Address
   execute  Data
   execute  Write_Enable_true
   execute  Clock_1
   execute  Write_Enable_false
end sub

sub   Write_false (Address,Data)
   execute  Address
   execute  Data
   execute  Write_Enable_false
   execute  Clock_1
   execute  Write_Enable_false
end sub

sub   Read  (Address,Data)
   execute  Address
   execute  Output_Store_true
   execute  Data
   execute  Output_Store_false
end sub

sub   Read_Store_false  (Address,Data)
   execute  Address
   execute  Output_Store_false
   execute  Data
   execute  Output_Store_false
end sub

sub   Read_Output_Disabled (Address,Data)
   execute  Address
   execute Output_Disable_True
   execute  Output_Store_true
   execute  Data
   execute  Output_Store_false
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutines reference the entire data bus.
!AT Therefore the subroutines were copied and modified to reference only
!AT a single pin of the data bus.

sub   Write_Dx (Address,Data,WE_t_Dx,Clk1_Dx,WE_f_Dx)
   execute  Address
   execute  Data
   execute  WE_t_Dx
   execute  Clk1_Dx
   execute  WE_f_Dx
end sub

sub   Read_Dx  (Address,Data,OS_t_Dx,OS_f_Dx)
   execute  Address
   execute  OS_t_Dx
   execute  Data
   execute  OS_f_Dx
end sub

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"
   execute Initialize_Inputs_D0
   call Write_Dx (Address_0000_D0, D0_I_0, WE_t_D0, Clk1_D0, WE_f_D0)
   call Read_Dx (Address_0000_D0, D0_O_0, OS_t_D0, OS_f_D0)

   call Write_Dx (Address_0000_D0, D0_I_1, WE_t_D0, Clk1_D0, WE_f_D0)
   call Read_Dx (Address_0000_D0, D0_O_1, OS_t_D0, OS_f_D0)
end unit

unit   "awaretest D1 Test"
   execute Initialize_Inputs_D1
   call Write_Dx (Address_0000_D1, D1_I_0, WE_t_D1, Clk1_D1, WE_f_D1)
   call Read_Dx (Address_0000_D1, D1_O_0, OS_t_D1, OS_f_D1)

   call Write_Dx (Address_0000_D1, D1_I_1, WE_t_D1, Clk1_D1, WE_f_D1)
   call Read_Dx (Address_0000_D1, D1_O_1, OS_t_D1, OS_f_D1)
end unit

unit   "awaretest D2 Test"
   execute Initialize_Inputs_D2
   call Write_Dx (Address_0000_D2, D2_I_0, WE_t_D2, Clk1_D2, WE_f_D2)
   call Read_Dx (Address_0000_D2, D2_O_0, OS_t_D2, OS_f_D2)

   call Write_Dx (Address_0000_D2, D2_I_1, WE_t_D2, Clk1_D2, WE_f_D2)
   call Read_Dx (Address_0000_D2, D2_O_1, OS_t_D2, OS_f_D2)
end unit

unit   "awaretest D3 Test"
   execute Initialize_Inputs_D3
   call Write_Dx (Address_0000_D3, D3_I_0, WE_t_D3, Clk1_D3, WE_f_D3)
   call Read_Dx (Address_0000_D3, D3_O_0, OS_t_D3, OS_f_D3)

   call Write_Dx (Address_0000_D3, D3_I_1, WE_t_D3, Clk1_D3, WE_f_D3)
   call Read_Dx (Address_0000_D3, D3_O_1, OS_t_D3, OS_f_D3)
end unit

unit  "Test Inputs"
   execute Initialize_Inputs
   call Write (Address_0000,Data_Inputs_0001)
   call Write (Address_0001,Data_Inputs_0010)
   call Write (Address_0010,Data_Inputs_0011)
   call Write (Address_0011,Data_Inputs_0100)
   call Write (Address_0100,Data_Inputs_0101)
   call Write (Address_0101,Data_Inputs_0101)
   call Write (Address_0110,Data_Inputs_0110)
   call Write (Address_0111,Data_Inputs_0111)
   call Write (Address_1000,Data_Inputs_1001)
   call Write (Address_1001,Data_Inputs_1010)
   call Write (Address_1010,Data_Inputs_1011)
   call Write (Address_1011,Data_Inputs_1100)
   call Write (Address_1100,Data_Inputs_1101)
   call Write (Address_1101,Data_Inputs_1101)
   call Write (Address_1110,Data_Inputs_1110)
   call Write (Address_1111,Data_Inputs_1111)

   call Read (Address_0000,Data_Outputs_0001)
   call Read (Address_0001,Data_Outputs_0010)
   call Read (Address_0010,Data_Outputs_0011)
   call Read (Address_0011,Data_Outputs_0100)
   call Read (Address_0100,Data_Outputs_0101)
   call Read (Address_0101,Data_Outputs_0101)
   call Read (Address_0110,Data_Outputs_0110)
   call Read (Address_0111,Data_Outputs_0111)
   call Read (Address_1000,Data_Outputs_1001)
   call Read (Address_1001,Data_Outputs_1010)
   call Read (Address_1010,Data_Outputs_1011)
   call Read (Address_1011,Data_Outputs_1100)
   call Read (Address_1100,Data_Outputs_1101)
   call Read (Address_1101,Data_Outputs_1101)
   call Read (Address_1110,Data_Outputs_1110)
   call Read (Address_1111,Data_Outputs_1111)
end unit

unit  "Test Write Enable "
   execute Initialize_Inputs
   call Write (Address_0000,Data_Inputs_0001)
   call Read (Address_0000,Data_Outputs_0001)
   call Write_false (Address_0000,Data_Inputs_1110)
   call Read (Address_0000,Data_Outputs_0001)
end unit

unit  "Test Output Store "
   execute Initialize_Inputs
   call Write (Address_0000,Data_Inputs_0001)
   call Read (Address_0000,Data_Outputs_0001)
   call Write (Address_0000,Data_Inputs_1110)
   call Read_Store_false (Address_0000,Data_Outputs_0001)
end unit

unit  "Test Output Disable"
   execute Initialize_Inputs
   call Write (Address_0000,Data_Inputs_0001)
   call Read_Output_Disabled (Address_0000,Data_Outputs_HIZ)
end unit


!End of test