!!!!    6    0    1  990201010  Vea90                                         

! Device           : am2947
! Function         : octal three-state bidirectional bus transceivers
! revision         : B.01.00
! safeguard        : high_out_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

!safeguard  high_out_ttl

! warning  "Pull-up resistors are required to test high-impedance outputs."

combinatorial

assign   VCC         to pins  20
assign   GND         to pins  10

assign   A_Inputs             to pins 1,2,3,4,5,6,7,8
assign   A_In_D0              to pins 8   !AT Added for minimum pin test.
assign   A_In_D1              to pins 7   !AT Added for minimum pin test.
assign   A_In_D2              to pins 6   !AT Added for minimum pin test.
assign   A_In_D3              to pins 5   !AT Added for minimum pin test.
assign   A_In_D4              to pins 4   !AT Added for minimum pin test.
assign   A_In_D5              to pins 3   !AT Added for minimum pin test.
assign   A_In_D6              to pins 2   !AT Added for minimum pin test.
assign   A_In_D7              to pins 1   !AT Added for minimum pin test.

assign   B_Inputs             to pins 19,18,17,16,15,14,13,12
assign   B_In_D0              to pins 12  !AT Added for minimum pin test.
assign   B_In_D1              to pins 13  !AT Added for minimum pin test.
assign   B_In_D2              to pins 14  !AT Added for minimum pin test.
assign   B_In_D3              to pins 15  !AT Added for minimum pin test.
assign   B_In_D4              to pins 16  !AT Added for minimum pin test.
assign   B_In_D5              to pins 17  !AT Added for minimum pin test.
assign   B_In_D6              to pins 18  !AT Added for minimum pin test.
assign   B_In_D7              to pins 19  !AT Added for minimum pin test.

assign   Transmit_Receive     to pins 11
assign   Chip_Disable         to pins 9

assign   A_Outputs            to pins 1,2,3,4,5,6,7,8
assign   A_Out_D0             to pins 8   !AT Added for minimum pin test.
assign   A_Out_D1             to pins 7   !AT Added for minimum pin test.
assign   A_Out_D2             to pins 6   !AT Added for minimum pin test.
assign   A_Out_D3             to pins 5   !AT Added for minimum pin test.
assign   A_Out_D4             to pins 4   !AT Added for minimum pin test.
assign   A_Out_D5             to pins 3   !AT Added for minimum pin test.
assign   A_Out_D6             to pins 2   !AT Added for minimum pin test.
assign   A_Out_D7             to pins 1   !AT Added for minimum pin test.

assign   B_Outputs            to pins 19,18,17,16,15,14,13,12
assign   B_Out_D0             to pins 12  !AT Added for minimum pin test.
assign   B_Out_D1             to pins 13  !AT Added for minimum pin test.
assign   B_Out_D2             to pins 14  !AT Added for minimum pin test.
assign   B_Out_D3             to pins 15  !AT Added for minimum pin test.
assign   B_Out_D4             to pins 16  !AT Added for minimum pin test.
assign   B_Out_D5             to pins 17  !AT Added for minimum pin test.
assign   B_Out_D6             to pins 18  !AT Added for minimum pin test.
assign   B_Out_D7             to pins 19  !AT Added for minimum pin test.

family   TTL

power    VCC,GND

inputs   Transmit_Receive, Chip_Disable

bidirectional  A_Inputs, B_Inputs, A_Outputs, B_Outputs
bidirectional A_In_D0,A_In_D1,A_In_D2,A_In_D3 !AT Added for minimum pin test.
bidirectional A_In_D4,A_In_D5,A_In_D6,A_In_D7 !AT Added for minimum pin test.
bidirectional A_Out_D0,A_Out_D1,A_Out_D2,A_Out_D3!AT Added for minimum pin test.
bidirectional A_Out_D4,A_Out_D5,A_Out_D6,A_Out_D7!AT Added for minimum pin test.
bidirectional B_In_D0,B_In_D1,B_In_D2,B_In_D3 !AT Added for minimum pin test.
bidirectional B_In_D4,B_In_D5,B_In_D6,B_In_D7 !AT Added for minimum pin test.
bidirectional B_Out_D0,B_Out_D1,B_Out_D2,B_Out_D3!AT Added for minimum pin test.
bidirectional B_Out_D4,B_Out_D5,B_Out_D6,B_Out_D7!AT Added for minimum pin test.

disable  A_Outputs with Transmit_Receive to "1"
disable  B_Outputs with Transmit_Receive to "0"

disable  A_Outputs with Chip_Disable to "1"
disable  B_Outputs with Chip_Disable to "1"

when     Transmit_Receive is "1" inputs A_Inputs
when     Transmit_Receive is "1" outputs B_Outputs
when     Transmit_Receive is "0" inputs B_Inputs
when     Transmit_Receive is "0" outputs A_Outputs

trace    A_Outputs to B_Inputs, Transmit_Receive, Chip_Disable
trace    B_Outputs to A_Inputs, Transmit_Receive, Chip_Disable

!***************************************************************
!***************************************************************

vector   Initialize_A_Inputs
   drive A_Inputs
   receive B_Outputs
   set   A_Inputs             to "00000000"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Keep_A_Inputs
   drive A_Inputs
   receive B_Outputs
   set   A_Inputs             to "kkkkkkkk"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Initialize_B_Inputs
   drive B_Inputs
   receive A_Outputs
   set   B_Inputs             to "00000000"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Keep_B_Inputs
   drive B_Inputs
   receive A_Outputs
   set   B_Inputs             to "kkkkkkkk"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   A_Inputs_00000000
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00000000"
end vector

vector   A_Inputs_00000001
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00000001"
end vector

vector   A_Inputs_00000011
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00000011"
end vector

vector   A_Inputs_00000111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00000111"
end vector

vector   A_Inputs_00001111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00001111"
end vector

vector   A_Inputs_00011111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00011111"
end vector

vector   A_Inputs_00111111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "00111111"
end vector

vector   A_Inputs_01111111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "01111111"
end vector

vector   A_Inputs_11111111
   initialize                 to Keep_A_Inputs
   set   A_Inputs             to "11111111"
end vector

vector   B_Inputs_00000000
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00000000"
end vector

vector   B_Inputs_00000001
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00000001"
end vector

vector   B_Inputs_00000011
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00000011"
end vector

vector   B_Inputs_00000111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00000111"
end vector

vector   B_Inputs_00001111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00001111"
end vector

vector   B_Inputs_00011111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00011111"
end vector

vector   B_Inputs_00111111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "00111111"
end vector

vector   B_Inputs_01111111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "01111111"
end vector

vector   B_Inputs_11111111
   initialize                 to Keep_B_Inputs
   set   B_Inputs             to "11111111"
end vector

vector   A_Outputs_00000000
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00000000"
end vector

vector   A_Outputs_00000001
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00000001"
end vector

vector   A_Outputs_00000011
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00000011"
end vector

vector   A_Outputs_00000111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00000111"
end vector

vector   A_Outputs_00001111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00001111"
end vector

vector   A_Outputs_00011111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00011111"
end vector

vector   A_Outputs_00111111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "00111111"
end vector

vector   A_Outputs_01111111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "01111111"
end vector

vector   A_Outputs_11111111
   initialize                 to Keep_B_Inputs
   set   A_Outputs            to "11111111"
end vector
vector   B_Outputs_00000000
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00000000"
end vector

vector   B_Outputs_00000001
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00000001"
end vector

vector   B_Outputs_00000011
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00000011"
end vector

vector   B_Outputs_00000111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00000111"
end vector

vector   B_Outputs_00001111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00001111"
end vector

vector   B_Outputs_00011111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00011111"
end vector

vector   B_Outputs_00111111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "00111111"
end vector

vector   B_Outputs_01111111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "01111111"
end vector

vector   B_Outputs_11111111
   initialize                 to Keep_A_Inputs
   set   B_Outputs            to "11111111"
end vector

vector   Chip_Disable_true_A
   initialize                 to Keep_A_Inputs
   set   Chip_Disable         to "1"
end vector

vector   Chip_Disable_true_B
   initialize                 to Keep_B_Inputs
   set   Chip_Disable         to "1"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Initialize_A_Inputs_D0
   drive A_In_D0
   receive B_Out_D0
   set   A_In_D0              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D1
   drive A_In_D1
   receive B_Out_D1
   set   A_In_D1              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D2
   drive A_In_D2
   receive B_Out_D2
   set   A_In_D2              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D3
   drive A_In_D3
   receive B_Out_D3
   set   A_In_D3              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D4
   drive A_In_D4
   receive B_Out_D4
   set   A_In_D4              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D5
   drive A_In_D5
   receive B_Out_D5
   set   A_In_D5              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D6
   drive A_In_D6
   receive B_Out_D6
   set   A_In_D6              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_A_Inputs_D7
   drive A_In_D7
   receive B_Out_D7
   set   A_In_D7              to "0"
   set   Transmit_Receive     to "1"
   set   Chip_Disable         to "0"
end vector

vector   Keep_A_Inputs_D0
   drive A_In_D0
   receive B_Out_D0
   set   A_In_D0              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D1
   drive A_In_D1
   receive B_Out_D1
   set   A_In_D1              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D2
   drive A_In_D2
   receive B_Out_D2
   set   A_In_D2              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D3
   drive A_In_D3
   receive B_Out_D3
   set   A_In_D3              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D4
   drive A_In_D4
   receive B_Out_D4
   set   A_In_D4              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D5
   drive A_In_D5
   receive B_Out_D5
   set   A_In_D5              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D6
   drive A_In_D6
   receive B_Out_D6
   set   A_In_D6              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_A_Inputs_D7
   drive A_In_D7
   receive B_Out_D7
   set   A_In_D7              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Initialize_B_Inputs_D0
   drive B_In_D0
   receive A_Out_D0
   set   B_In_D0              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D1
   drive B_In_D1
   receive A_Out_D1
   set   B_In_D1              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D2
   drive B_In_D2
   receive A_Out_D2
   set   B_In_D2              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D3
   drive B_In_D3
   receive A_Out_D3
   set   B_In_D3              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D4
   drive B_In_D4
   receive A_Out_D4
   set   B_In_D4              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D5
   drive B_In_D5
   receive A_Out_D5
   set   B_In_D5              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D6
   drive B_In_D6
   receive A_Out_D6
   set   B_In_D6              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Initialize_B_Inputs_D7
   drive B_In_D7
   receive A_Out_D7
   set   B_In_D7              to "0"
   set   Transmit_Receive     to "0"
   set   Chip_Disable         to "0"
end vector

vector   Keep_B_Inputs_D0
   drive B_In_D0
   receive A_Out_D0
   set   B_In_D0              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D1
   drive B_In_D1
   receive A_Out_D1
   set   B_In_D1              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D2
   drive B_In_D2
   receive A_Out_D2
   set   B_In_D2              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D3
   drive B_In_D3
   receive A_Out_D3
   set   B_In_D3              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D4
   drive B_In_D4
   receive A_Out_D4
   set   B_In_D4              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D5
   drive B_In_D5
   receive A_Out_D5
   set   B_In_D5              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D6
   drive B_In_D6
   receive A_Out_D6
   set   B_In_D6              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   Keep_B_Inputs_D7
   drive B_In_D7
   receive A_Out_D7
   set   B_In_D7              to "k"
   set   Transmit_Receive     to "k"
   set   Chip_Disable         to "k"
end vector

vector   A_Inputs_D0_0
   initialize                 to Keep_A_Inputs_D0
   set   A_In_D0              to "0"
end vector

vector   A_Inputs_D0_1
   initialize                 to Keep_A_Inputs_D0
   set   A_In_D0              to "1"
end vector

vector   A_Inputs_D1_0
   initialize                 to Keep_A_Inputs_D1
   set   A_In_D1              to "0"
end vector

vector   A_Inputs_D1_1
   initialize                 to Keep_A_Inputs_D1
   set   A_In_D1              to "1"
end vector

vector   A_Inputs_D2_0
   initialize                 to Keep_A_Inputs_D2
   set   A_In_D2              to "0"
end vector

vector   A_Inputs_D2_1
   initialize                 to Keep_A_Inputs_D2
   set   A_In_D2              to "1"
end vector

vector   A_Inputs_D3_0
   initialize                 to Keep_A_Inputs_D3
   set   A_In_D3              to "0"
end vector

vector   A_Inputs_D3_1
   initialize                 to Keep_A_Inputs_D3
   set   A_In_D3              to "1"
end vector

vector   A_Inputs_D4_0
   initialize                 to Keep_A_Inputs_D4
   set   A_In_D4              to "0"
end vector

vector   A_Inputs_D4_1
   initialize                 to Keep_A_Inputs_D4
   set   A_In_D4              to "1"
end vector

vector   A_Inputs_D5_0
   initialize                 to Keep_A_Inputs_D5
   set   A_In_D5              to "0"
end vector

vector   A_Inputs_D5_1
   initialize                 to Keep_A_Inputs_D5
   set   A_In_D5              to "1"
end vector

vector   A_Inputs_D6_0
   initialize                 to Keep_A_Inputs_D6
   set   A_In_D6              to "0"
end vector

vector   A_Inputs_D6_1
   initialize                 to Keep_A_Inputs_D6
   set   A_In_D6              to "1"
end vector

vector   A_Inputs_D7_0
   initialize                 to Keep_A_Inputs_D7
   set   A_In_D7              to "0"
end vector

vector   A_Inputs_D7_1
   initialize                 to Keep_A_Inputs_D7
   set   A_In_D7              to "1"
end vector

vector   B_Inputs_D0_0
   initialize                 to Keep_B_Inputs_D0
   set   B_In_D0              to "0"
end vector

vector   B_Inputs_D0_1
   initialize                 to Keep_B_Inputs_D0
   set   B_In_D0              to "1"
end vector

vector   B_Inputs_D1_0
   initialize                 to Keep_B_Inputs_D1
   set   B_In_D1              to "0"
end vector

vector   B_Inputs_D1_1
   initialize                 to Keep_B_Inputs_D1
   set   B_In_D1              to "1"
end vector

vector   B_Inputs_D2_0
   initialize                 to Keep_B_Inputs_D2
   set   B_In_D2              to "0"
end vector

vector   B_Inputs_D2_1
   initialize                 to Keep_B_Inputs_D2
   set   B_In_D2              to "1"
end vector

vector   B_Inputs_D3_0
   initialize                 to Keep_B_Inputs_D3
   set   B_In_D3              to "0"
end vector

vector   B_Inputs_D3_1
   initialize                 to Keep_B_Inputs_D3
   set   B_In_D3              to "1"
end vector

vector   B_Inputs_D4_0
   initialize                 to Keep_B_Inputs_D4
   set   B_In_D4              to "0"
end vector

vector   B_Inputs_D4_1
   initialize                 to Keep_B_Inputs_D4
   set   B_In_D4              to "1"
end vector

vector   B_Inputs_D5_0
   initialize                 to Keep_B_Inputs_D5
   set   B_In_D5              to "0"
end vector

vector   B_Inputs_D5_1
   initialize                 to Keep_B_Inputs_D5
   set   B_In_D5              to "1"
end vector

vector   B_Inputs_D6_0
   initialize                 to Keep_B_Inputs_D6
   set   B_In_D6              to "0"
end vector

vector   B_Inputs_D6_1
   initialize                 to Keep_B_Inputs_D6
   set   B_In_D6              to "1"
end vector

vector   B_Inputs_D7_0
   initialize                 to Keep_B_Inputs_D7
   set   B_In_D7              to "0"
end vector

vector   B_Inputs_D7_1
   initialize                 to Keep_B_Inputs_D7
   set   B_In_D7              to "1"
end vector

vector   A_Outputs_D0_0
   initialize                 to Keep_B_Inputs_D0
   set   A_Out_D0             to "0"
end vector

vector   A_Outputs_D0_1
   initialize                 to Keep_B_Inputs_D0
   set   A_Out_D0             to "1"
end vector

vector   A_Outputs_D1_0
   initialize                 to Keep_B_Inputs_D1
   set   A_Out_D1             to "0"
end vector

vector   A_Outputs_D1_1
   initialize                 to Keep_B_Inputs_D1
   set   A_Out_D1             to "1"
end vector

vector   A_Outputs_D2_0
   initialize                 to Keep_B_Inputs_D2
   set   A_Out_D2             to "0"
end vector

vector   A_Outputs_D2_1
   initialize                 to Keep_B_Inputs_D2
   set   A_Out_D2             to "1"
end vector

vector   A_Outputs_D3_0
   initialize                 to Keep_B_Inputs_D3
   set   A_Out_D3             to "0"
end vector

vector   A_Outputs_D3_1
   initialize                 to Keep_B_Inputs_D3
   set   A_Out_D3             to "1"
end vector

vector   A_Outputs_D4_0
   initialize                 to Keep_B_Inputs_D4
   set   A_Out_D4             to "0"
end vector

vector   A_Outputs_D4_1
   initialize                 to Keep_B_Inputs_D4
   set   A_Out_D4             to "1"
end vector

vector   A_Outputs_D5_0
   initialize                 to Keep_B_Inputs_D5
   set   A_Out_D5             to "0"
end vector

vector   A_Outputs_D5_1
   initialize                 to Keep_B_Inputs_D5
   set   A_Out_D5             to "1"
end vector

vector   A_Outputs_D6_0
   initialize                 to Keep_B_Inputs_D6
   set   A_Out_D6             to "0"
end vector

vector   A_Outputs_D6_1
   initialize                 to Keep_B_Inputs_D6
   set   A_Out_D6             to "1"
end vector

vector   A_Outputs_D7_0
   initialize                 to Keep_B_Inputs_D7
   set   A_Out_D7             to "0"
end vector

vector   A_Outputs_D7_1
   initialize                 to Keep_B_Inputs_D7
   set   A_Out_D7             to "1"
end vector

vector   B_Outputs_D0_0
   initialize                 to Keep_A_Inputs_D0
   set   B_Out_D0             to "0"
end vector

vector   B_Outputs_D0_1
   initialize                 to Keep_A_Inputs_D0
   set   B_Out_D0             to "1"
end vector

vector   B_Outputs_D1_0
   initialize                 to Keep_A_Inputs_D1
   set   B_Out_D1             to "0"
end vector

vector   B_Outputs_D1_1
   initialize                 to Keep_A_Inputs_D1
   set   B_Out_D1             to "1"
end vector

vector   B_Outputs_D2_0
   initialize                 to Keep_A_Inputs_D2
   set   B_Out_D2             to "0"
end vector

vector   B_Outputs_D2_1
   initialize                 to Keep_A_Inputs_D2
   set   B_Out_D2             to "1"
end vector

vector   B_Outputs_D3_0
   initialize                 to Keep_A_Inputs_D3
   set   B_Out_D3             to "0"
end vector

vector   B_Outputs_D3_1
   initialize                 to Keep_A_Inputs_D3
   set   B_Out_D3             to "1"
end vector

vector   B_Outputs_D4_0
   initialize                 to Keep_A_Inputs_D4
   set   B_Out_D4             to "0"
end vector

vector   B_Outputs_D4_1
   initialize                 to Keep_A_Inputs_D4
   set   B_Out_D4             to "1"
end vector

vector   B_Outputs_D5_0
   initialize                 to Keep_A_Inputs_D5
   set   B_Out_D5             to "0"
end vector

vector   B_Outputs_D5_1
   initialize                 to Keep_A_Inputs_D5
   set   B_Out_D5             to "1"
end vector

vector   B_Outputs_D6_0
   initialize                 to Keep_A_Inputs_D6
   set   B_Out_D6             to "0"
end vector

vector   B_Outputs_D6_1
   initialize                 to Keep_A_Inputs_D6
   set   B_Out_D6             to "1"
end vector

vector   B_Outputs_D7_0
   initialize                 to Keep_A_Inputs_D7
   set   B_Out_D7             to "0"
end vector

vector   B_Outputs_D7_1
   initialize                 to Keep_A_Inputs_D7
   set   B_Out_D7             to "1"
end vector


!***************************************************************
!***************************************************************

sub   Transceive (Inputs, Outputs)
   execute  Inputs
   execute  Outputs
end sub

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit  "awaretest Test A_Inputs_D0 and B_Outputs_D0"
   execute Initialize_A_Inputs_D0
   call Transceive (A_Inputs_D0_0, B_Outputs_D0_0)
   call Transceive (A_Inputs_D0_1, B_Outputs_D0_1)
end unit

unit  "awaretest Test A_Inputs_D1 and B_Outputs_D1"
   execute Initialize_A_Inputs_D1
   call Transceive (A_Inputs_D1_0, B_Outputs_D1_0)
   call Transceive (A_Inputs_D1_1, B_Outputs_D1_1)
end unit

unit  "awaretest Test A_Inputs_D2 and B_Outputs_D2"
   execute Initialize_A_Inputs_D2
   call Transceive (A_Inputs_D2_0, B_Outputs_D2_0)
   call Transceive (A_Inputs_D2_1, B_Outputs_D2_1)
end unit

unit  "awaretest Test A_Inputs_D3 and B_Outputs_D3"
   execute Initialize_A_Inputs_D3
   call Transceive (A_Inputs_D3_0, B_Outputs_D3_0)
   call Transceive (A_Inputs_D3_1, B_Outputs_D3_1)
end unit

unit  "awaretest Test A_Inputs_D4 and B_Outputs_D4"
   execute Initialize_A_Inputs_D4
   call Transceive (A_Inputs_D4_0, B_Outputs_D4_0)
   call Transceive (A_Inputs_D4_1, B_Outputs_D4_1)
end unit

unit  "awaretest Test A_Inputs_D5 and B_Outputs_D5"
   execute Initialize_A_Inputs_D5
   call Transceive (A_Inputs_D5_0, B_Outputs_D5_0)
   call Transceive (A_Inputs_D5_1, B_Outputs_D5_1)
end unit

unit  "awaretest Test A_Inputs_D6 and B_Outputs_D6"
   execute Initialize_A_Inputs_D6
   call Transceive (A_Inputs_D6_0, B_Outputs_D6_0)
   call Transceive (A_Inputs_D6_1, B_Outputs_D6_1)
end unit

unit  "awaretest Test A_Inputs_D7 and B_Outputs_D7"
   execute Initialize_A_Inputs_D7
   call Transceive (A_Inputs_D7_0, B_Outputs_D7_0)
   call Transceive (A_Inputs_D7_1, B_Outputs_D7_1)
end unit

unit  "awaretest Test B_Inputs_D0 and A_Outputs_D0"
   execute Initialize_B_Inputs_D0
   call Transceive (B_Inputs_D0_0, A_Outputs_D0_0)
   call Transceive (B_Inputs_D0_1, A_Outputs_D0_1)
end unit

unit  "awaretest Test B_Inputs_D1 and A_Outputs_D1"
   execute Initialize_B_Inputs_D1
   call Transceive (B_Inputs_D1_0, A_Outputs_D1_0)
   call Transceive (B_Inputs_D1_1, A_Outputs_D1_1)
end unit

unit  "awaretest Test B_Inputs_D2 and A_Outputs_D2"
   execute Initialize_B_Inputs_D2
   call Transceive (B_Inputs_D2_0, A_Outputs_D2_0)
   call Transceive (B_Inputs_D2_1, A_Outputs_D2_1)
end unit

unit  "awaretest Test B_Inputs_D3 and A_Outputs_D3"
   execute Initialize_B_Inputs_D3
   call Transceive (B_Inputs_D3_0, A_Outputs_D3_0)
   call Transceive (B_Inputs_D3_1, A_Outputs_D3_1)
end unit

unit  "awaretest Test B_Inputs_D4 and A_Outputs_D4"
   execute Initialize_B_Inputs_D4
   call Transceive (B_Inputs_D4_0, A_Outputs_D4_0)
   call Transceive (B_Inputs_D4_1, A_Outputs_D4_1)
end unit

unit  "awaretest Test B_Inputs_D5 and A_Outputs_D5"
   execute Initialize_B_Inputs_D5
   call Transceive (B_Inputs_D5_0, A_Outputs_D5_0)
   call Transceive (B_Inputs_D5_1, A_Outputs_D5_1)
end unit

unit  "awaretest Test B_Inputs_D6 and A_Outputs_D6"
   execute Initialize_B_Inputs_D6
   call Transceive (B_Inputs_D6_0, A_Outputs_D6_0)
   call Transceive (B_Inputs_D6_1, A_Outputs_D6_1)
end unit

unit  "awaretest Test B_Inputs_D7 and A_Outputs_D7"
   execute Initialize_B_Inputs_D7
   call Transceive (B_Inputs_D7_0, A_Outputs_D7_0)
   call Transceive (B_Inputs_D7_1, A_Outputs_D7_1)
end unit

unit  "Test A_Inputs and B_Outputs"
   execute Initialize_A_Inputs
   call Transceive (A_Inputs_00000000, B_Outputs_00000000)
   call Transceive (A_Inputs_00000001, B_Outputs_00000001)
   call Transceive (A_Inputs_00000011, B_Outputs_00000011)
   call Transceive (A_Inputs_00000111, B_Outputs_00000111)
   call Transceive (A_Inputs_00001111, B_Outputs_00001111)
   call Transceive (A_Inputs_00011111, B_Outputs_00011111)
   call Transceive (A_Inputs_00111111, B_Outputs_00111111)
   call Transceive (A_Inputs_01111111, B_Outputs_01111111)
   call Transceive (A_Inputs_11111111, B_Outputs_11111111)
end unit

unit  "Test B_Inputs and A_Outputs"
   execute Initialize_B_Inputs
   call Transceive (B_Inputs_00000000, A_Outputs_00000000)
   call Transceive (B_Inputs_00000001, A_Outputs_00000001)
   call Transceive (B_Inputs_00000011, A_Outputs_00000011)
   call Transceive (B_Inputs_00000111, A_Outputs_00000111)
   call Transceive (B_Inputs_00001111, A_Outputs_00001111)
   call Transceive (B_Inputs_00011111, A_Outputs_00011111)
   call Transceive (B_Inputs_00111111, A_Outputs_00111111)
   call Transceive (B_Inputs_01111111, A_Outputs_01111111)
   call Transceive (B_Inputs_11111111, A_Outputs_11111111)
end unit

!unit  "Test Chip_Disable and High-Impedance B_Outputs"
!   execute Initialize_A_Inputs
!   execute Chip_Disable_true_A
!   call Transceive (A_Inputs_00000000, B_Outputs_11111111)
!end unit

!unit  "Test Chip_Disable and High-Impedance A_Outputs"
!   execute Initialize_B_Inputs
!   execute Chip_Disable_true_B
!   call Transceive (B_Inputs_00000000, A_Outputs_11111111)
!end unit


!End of test