!!!!    6    0    1  990666360  Vc49f                                         

! Device           : 2905
! Function         : Quad Two-Input OC Bus Transceiver with 3-State Receiver
! revision         : B.01.00
! safeguard        : hi_oc_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

vector cycle 2000n
receive delay 1900n

assign      VCC                to pins       24
assign      GND                to pins       6,18

assign      A_3210             to pins       20,16,8,4
assign      A0_I        to pins   4         !AT Added for minimum pin test.
assign      A1_I        to pins   8         !AT Added for minimum pin test.
assign      A2_I        to pins   16        !AT Added for minimum pin test.
assign      A3_I        to pins   20        !AT Added for minimum pin test.

assign      B_3210             to pins       21,15,9,3
assign      B0_I        to pins   3         !AT Added for minimum pin test.
assign      B1_I        to pins   9         !AT Added for minimum pin test.
assign      B2_I        to pins   15        !AT Added for minimum pin test.
assign      B3_I        to pins   21        !AT Added for minimum pin test.

assign      R_3210             to pins       22,14,10,2
assign      R0_O        to pins   2         !AT Added for minimum pin test.
assign      R1_O        to pins   10        !AT Added for minimum pin test.
assign      R2_O        to pins   14        !AT Added for minimum pin test.
assign      R3_O        to pins   22        !AT Added for minimum pin test.

assign      BUS_bar            to pins       19,17,7,5
assign      Bus0        to pins   5         !AT Added for minimum pin test.
assign      Bus1        to pins   7         !AT Added for minimum pin test.
assign      Bus2        to pins   17        !AT Added for minimum pin test.
assign      Bus3        to pins   19        !AT Added for minimum pin test.

assign      RLE_bar            to pins       1
assign      Select             to pins       13
assign      DRCP               to pins       23
assign      BE_bar             to pins       11
assign      OE_bar             to pins       12

family      TTL

power       VCC, GND

inputs      A_3210, B_3210, Select, DRCP, BE_bar, OE_bar, RLE_bar
inputs      A0_I, A1_I, A2_I, A3_I         !AT Added for minimum pin test.
inputs      B0_I, B1_I, B2_I, B3_I         !AT Added for minimum pin test.

outputs     R_3210
outputs     R0_O, R1_O, R2_O, R3_O         !AT Added for minimum pin test.

bidirectional    BUS_bar
bidirectional    Bus0, Bus1, Bus2, Bus3    !AT Added for minimum pin test.

when     BE_bar   is    "1"   inputs   BUS_bar
when     BE_bar   is    "0"   outputs  BUS_bar

when     OE_bar   is    "1"   inactive R_3210

trace  R_3210 to  A_3210,B_3210,Select,DRCP,BE_bar,OE_bar,RLE_bar,BUS_bar

trace  BUS_bar to  A_3210,B_3210,Select,DRCP,BE_bar

disable     BUS_bar         with          BE_bar          to         "1"
disable     R_3210          with          OE_bar          to         "1"


!*****************************************************************************
!*****************************************************************************


vector      A_In_0000
set    Select             to            "0"
set    A_3210             to            "0000"
set    DRCP               to            "0"
end vector

vector      A_In_0001
set    Select             to            "0"
set    A_3210             to            "0001"
set    DRCP               to            "0"
end vector

vector      A_In_0011
set    Select             to            "0"
set    A_3210             to            "0011"
set    DRCP               to            "0"
end vector

vector      A_In_0111
set    Select             to            "0"
set    A_3210             to            "0111"
set    DRCP               to            "0"
end vector

vector      A_In_1111
set    Select             to            "0"
set    A_3210             to            "1111"
set    DRCP               to            "0"
end vector

vector      B_In_0000
set    Select             to            "1"
set    B_3210             to            "0000"
set    DRCP               to            "0"
end vector

vector      B_In_0001
set    Select             to            "1"
set    B_3210             to            "0001"
set    DRCP               to            "0"
end vector

vector      B_In_0011
set    Select             to            "1"
set    B_3210             to            "0011"
set    DRCP               to            "0"
end vector

vector      B_In_0111
set    Select             to            "1"
set    B_3210             to            "0111"
set    DRCP               to            "0"
end vector

vector      B_In_1111
set    Select             to            "1"
set    B_3210             to            "1111"
set    DRCP               to            "0"
end vector

vector      DRCP_high_A
set    Select             to            "0"
set    A_3210             to            "kkkk"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_B
set    Select             to            "1"
set    B_3210             to            "kkkk"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      Receive_Outputs_0000
receive Bus_bar
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus_bar            to            "1111"
set    R_3210             to            "0000"
end vector

vector      Receive_Outputs_0001
receive Bus_bar
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus_bar            to            "1110"
set    R_3210             to            "0001"
end vector

vector      Receive_Outputs_0011
receive Bus_bar
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus_bar            to            "1100"
set    R_3210             to            "0011"
end vector

vector      Receive_Outputs_0111
receive Bus_bar
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus_bar            to            "1000"
set    R_3210             to            "0111"
end vector

vector      Receive_Outputs_1111
receive Bus_bar
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus_bar            to            "0000"
set    R_3210             to            "1111"
end vector

vector      End_Receive_Cycle
set    DRCP               to            "1"
end vector

vector      BE_bar_false
set    Select             to            "0"
set    A_3210             to            "0000"
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      Drive_Bus_0101
initialize to BE_bar_false
drive Bus_bar
set    DRCP               to            "0"
set    Bus_bar            to            "0101"
end vector

vector      Drive_Bus_1010
initialize to BE_bar_false
drive Bus_bar
set    DRCP               to            "0"
set    Bus_bar            to            "1010"
end vector

vector      Clock_high
initialize to BE_bar_false
drive Bus_bar
set    DRCP               to            "1"
set    Bus_bar            to            "kkkk"
end vector

vector      Receive_1010
initialize to BE_bar_false
drive Bus_bar
set    DRCP               to            "0"
set    Bus_bar            to            "kkkk"
set    R_3210             to            "1010"
end vector

vector      Receive_0101
initialize to BE_bar_false
drive Bus_bar
set    DRCP               to            "0"
set    Bus_bar            to            "kkkk"
set    R_3210             to            "0101"
end vector

vector      Bus_in_0000
drive Bus_bar
set    RLE_bar            to            "0"
set    BE_bar             to            "1"
set    Bus_bar            to            "0000"
set    OE_bar             to            "0"
end vector

vector      Bus_in_0000_RLE_false
drive Bus_bar
set    RLE_bar            to            "1"
set    BE_bar             to            "1"
set    Bus_bar            to            "0000"
set    OE_bar             to            "0"
end vector

vector      Bus_In_1111_RLE_false
drive Bus_bar
set    BE_bar             to            "1"
set    RLE_bar            to            "1"
set    Bus_bar            to            "1111"
set    OE_bar             to            "0"
end vector

vector      Bus_in_1111
drive Bus_bar
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    Bus_bar            to            "1111"
set    OE_bar             to            "0"
end vector

vector      R_1111
drive Bus_bar
set    BE_bar             to            "1"
set    RLE_bar            to            "k"
set    Bus_bar            to            "kkkk"
set    OE_bar             to            "0"
set    R_3210             to            "1111"
end vector

vector      R_0000
drive Bus_bar
set    BE_bar             to            "1"
set    RLE_bar            to            "k"
set    Bus_bar            to            "kkkk"
set    OE_bar             to            "0"
set    R_3210             to            "0000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector      A0_In_0
set    Select             to            "0"
set    A0_I               to            "0"
set    DRCP               to            "0"
end vector

vector      A0_In_1
set    Select             to            "0"
set    A0_I               to            "1"
set    DRCP               to            "0"
end vector

vector      A1_In_0
set    Select             to            "0"
set    A1_I               to            "0"
set    DRCP               to            "0"
end vector

vector      A1_In_1
set    Select             to            "0"
set    A1_I               to            "1"
set    DRCP               to            "0"
end vector

vector      A2_In_0
set    Select             to            "0"
set    A2_I               to            "0"
set    DRCP               to            "0"
end vector

vector      A2_In_1
set    Select             to            "0"
set    A2_I               to            "1"
set    DRCP               to            "0"
end vector

vector      A3_In_0
set    Select             to            "0"
set    A3_I               to            "0"
set    DRCP               to            "0"
end vector

vector      A3_In_1
set    Select             to            "0"
set    A3_I               to            "1"
set    DRCP               to            "0"
end vector

vector      B0_In_0
set    Select             to            "1"
set    B0_I               to            "0"
set    DRCP               to            "0"
end vector

vector      B0_In_1
set    Select             to            "1"
set    B0_I               to            "1"
set    DRCP               to            "0"
end vector

vector      B1_In_0
set    Select             to            "1"
set    B1_I               to            "0"
set    DRCP               to            "0"
end vector

vector      B1_In_1
set    Select             to            "1"
set    B1_I               to            "1"
set    DRCP               to            "0"
end vector

vector      B2_In_0
set    Select             to            "1"
set    B2_I               to            "0"
set    DRCP               to            "0"
end vector

vector      B2_In_1
set    Select             to            "1"
set    B2_I               to            "1"
set    DRCP               to            "0"
end vector

vector      B3_In_0
set    Select             to            "1"
set    B3_I               to            "0"
set    DRCP               to            "0"
end vector

vector      B3_In_1
set    Select             to            "1"
set    B3_I               to            "1"
set    DRCP               to            "0"
end vector

vector      DRCP_high_A0
set    Select             to            "0"
set    A0_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_A1
set    Select             to            "0"
set    A1_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_A2
set    Select             to            "0"
set    A2_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_A3
set    Select             to            "0"
set    A3_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_B0
set    Select             to            "1"
set    B0_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_B1
set    Select             to            "1"
set    B1_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_B2
set    Select             to            "1"
set    B2_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      DRCP_high_B3
set    Select             to            "1"
set    B3_I               to            "k"
set    DRCP               to            "1"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      R0_Outputs_0
receive Bus0
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus0               to            "1"
set    R0_O               to            "0"
end vector

vector      R0_Outputs_1
receive Bus0
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus0               to            "0"
set    R0_O               to            "1"
end vector

vector      R1_Outputs_0
receive Bus1
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus1               to            "1"
set    R1_O               to            "0"
end vector

vector      R1_Outputs_1
receive Bus1
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus1               to            "0"
set    R1_O               to            "1"
end vector

vector      R2_Outputs_0
receive Bus2
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus2               to            "1"
set    R2_O               to            "0"
end vector

vector      R2_Outputs_1
receive Bus2
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus2               to            "0"
set    R2_O               to            "1"
end vector

vector      R3_Outputs_0
receive Bus3
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus3               to            "1"
set    R3_O               to            "0"
end vector

vector      R3_Outputs_1
receive Bus3
set    DRCP               to            "0"
set    BE_bar             to            "0"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
set    Bus3               to            "0"
set    R3_O               to            "1"
end vector

vector      BE_bar_false_A0
set    Select             to            "0"
set    A0_I               to            "0"
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      BE_bar_false_A1
set    Select             to            "0"
set    A1_I               to            "0"
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      BE_bar_false_A2
set    Select             to            "0"
set    A2_I               to            "0"
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      BE_bar_false_A3
set    Select             to            "0"
set    A3_I               to            "0"
set    BE_bar             to            "1"
set    RLE_bar            to            "0"
set    OE_bar             to            "0"
end vector

vector      Drive_Bus0_0
initialize to BE_bar_false_A0
drive Bus0
set    DRCP               to            "0"
set    Bus0               to            "0"
end vector

vector      Drive_Bus0_1
initialize to BE_bar_false_A0
drive Bus0
set    DRCP               to            "0"
set    Bus0               to            "1"
end vector

vector      Drive_Bus1_0
initialize to BE_bar_false_A1
drive Bus1
set    DRCP               to            "0"
set    Bus1               to            "0"
end vector

vector      Drive_Bus1_1
initialize to BE_bar_false_A1
drive Bus1
set    DRCP               to            "0"
set    Bus1               to            "1"
end vector

vector      Drive_Bus2_0
initialize to BE_bar_false_A2
drive Bus2
set    DRCP               to            "0"
set    Bus2               to            "0"
end vector

vector      Drive_Bus2_1
initialize to BE_bar_false_A2
drive Bus2
set    DRCP               to            "0"
set    Bus2               to            "1"
end vector

vector      Drive_Bus3_0
initialize to BE_bar_false_A3
drive Bus3
set    DRCP               to            "0"
set    Bus3               to            "0"
end vector

vector      Drive_Bus3_1
initialize to BE_bar_false_A3
drive Bus3
set    DRCP               to            "0"
set    Bus3               to            "1"
end vector

vector      Clock_high_Bus0
initialize to BE_bar_false_A0
drive Bus0
set    DRCP               to            "1"
set    Bus0               to            "k"
end vector

vector      Clock_high_Bus1
initialize to BE_bar_false_A1
drive Bus1
set    DRCP               to            "1"
set    Bus1               to            "k"
end vector

vector      Clock_high_Bus2
initialize to BE_bar_false_A2
drive Bus2
set    DRCP               to            "1"
set    Bus2               to            "k"
end vector

vector      Clock_high_Bus3
initialize to BE_bar_false_A3
drive Bus3
set    DRCP               to            "1"
set    Bus3               to            "k"
end vector

vector      R0_O_0
initialize to BE_bar_false_A0
drive Bus0
set    DRCP               to            "0"
set    Bus0               to            "k"
set    R0_O               to            "0"
end vector

vector      R0_O_1
initialize to BE_bar_false_A0
drive Bus0
set    DRCP               to            "0"
set    Bus0               to            "k"
set    R0_O               to            "1"
end vector

vector      R1_O_0
initialize to BE_bar_false_A1
drive Bus1
set    DRCP               to            "0"
set    Bus1               to            "k"
set    R1_O               to            "0"
end vector

vector      R1_O_1
initialize to BE_bar_false_A1
drive Bus1
set    DRCP               to            "0"
set    Bus1               to            "k"
set    R1_O               to            "1"
end vector

vector      R2_O_0
initialize to BE_bar_false_A2
drive Bus2
set    DRCP               to            "0"
set    Bus2               to            "k"
set    R2_O               to            "0"
end vector

vector      R2_O_1
initialize to BE_bar_false_A2
drive Bus2
set    DRCP               to            "0"
set    Bus2               to            "k"
set    R2_O               to            "1"
end vector

vector      R3_O_0
initialize to BE_bar_false_A3
drive Bus3
set    DRCP               to            "0"
set    Bus3               to            "k"
set    R3_O               to            "0"
end vector

vector      R3_O_1
initialize to BE_bar_false_A3
drive Bus3
set    DRCP               to            "0"
set    Bus3               to            "k"
set    R3_O               to            "1"
end vector


!*****************************************************************************
!*****************************************************************************


!    The following units tests for SA1 and SA0 on all pins except OE_bar,
!    which connot be tested for SA0.


sub         A_Inputs_Test (Input,Receive)
execute           Input
execute           DRCP_high_A
execute           Receive
execute           End_Receive_Cycle
end sub

sub         B_Inputs_Test (Input,Receive)
execute           Input
execute           DRCP_high_B
execute           Receive
execute           End_Receive_Cycle
end sub

!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with A0.

unit "awaretest A0 input Test"

execute           A0_In_0
execute           DRCP_high_A0
execute           R0_Outputs_0
execute           End_Receive_Cycle

execute           A0_In_1
execute           DRCP_high_A0
execute           R0_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest A1 input Test"

execute           A1_In_0
execute           DRCP_high_A1
execute           R1_Outputs_0
execute           End_Receive_Cycle

execute           A1_In_1
execute           DRCP_high_A1
execute           R1_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest A2 input Test"

execute           A2_In_0
execute           DRCP_high_A2
execute           R2_Outputs_0
execute           End_Receive_Cycle

execute           A2_In_1
execute           DRCP_high_A2
execute           R2_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest A3 input Test"

execute           A3_In_0
execute           DRCP_high_A3
execute           R3_Outputs_0
execute           End_Receive_Cycle

execute           A3_In_1
execute           DRCP_high_A3
execute           R3_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest B0 input Test"

execute           B0_In_0
execute           DRCP_high_B0
execute           R0_Outputs_0
execute           End_Receive_Cycle

execute           B0_In_1
execute           DRCP_high_B0
execute           R0_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest B1 input Test"

execute           B1_In_0
execute           DRCP_high_B1
execute           R1_Outputs_0
execute           End_Receive_Cycle

execute           B1_In_1
execute           DRCP_high_B1
execute           R1_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest B2 input Test"

execute           B2_In_0
execute           DRCP_high_B2
execute           R2_Outputs_0
execute           End_Receive_Cycle

execute           B2_In_1
execute           DRCP_high_B2
execute           R2_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest B3 input Test"

execute           B3_In_0
execute           DRCP_high_B3
execute           R3_Outputs_0
execute           End_Receive_Cycle

execute           B3_In_1
execute           DRCP_high_B3
execute           R3_Outputs_1
execute           End_Receive_Cycle

end unit

unit "awaretest Bus0 Test"

execute           Drive_Bus0_1
execute           Clock_high_Bus0
execute           R0_O_0
execute           Drive_Bus0_0
execute           Clock_high_Bus0
execute           R0_O_1

end unit

unit "awaretest Bus1 Test"

execute           Drive_Bus1_1
execute           Clock_high_Bus1
execute           R1_O_0
execute           Drive_Bus1_0
execute           Clock_high_Bus1
execute           R1_O_1

end unit

unit "awaretest Bus2 Test"

execute           Drive_Bus2_1
execute           Clock_high_Bus2
execute           R2_O_0
execute           Drive_Bus2_0
execute           Clock_high_Bus2
execute           R2_O_1

end unit

unit "awaretest Bus3 Test"

execute           Drive_Bus3_1
execute           Clock_high_Bus3
execute           R3_O_0
execute           Drive_Bus3_0
execute           Clock_high_Bus3
execute           R3_O_1

end unit


unit        "Test A_Inputs"

call              A_Inputs_Test (A_In_0000,Receive_Outputs_0000)
call              A_Inputs_Test (A_In_0001,Receive_Outputs_0001)
call              A_Inputs_Test (A_In_0011,Receive_Outputs_0011)
call              A_Inputs_Test (A_In_0111,Receive_Outputs_0111)
call              A_Inputs_Test (A_In_1111,Receive_Outputs_1111)

end unit


unit        "Test B_Inputs"

call              B_Inputs_Test (B_In_0000,Receive_Outputs_0000)
call              B_Inputs_Test (B_In_0001,Receive_Outputs_0001)
call              B_Inputs_Test (B_In_0011,Receive_Outputs_0011)
call              B_Inputs_Test (B_In_0111,Receive_Outputs_0111)
call              B_Inputs_Test (B_In_1111,Receive_Outputs_1111)

end unit


unit        "Bus Inputs Test"

execute           Drive_bus_0101
execute           Clock_high
execute           Receive_1010
execute           Drive_bus_1010
execute           Clock_high
execute           Receive_0101

end unit


unit        "RLE_bar Test"

execute           Bus_In_0000
execute           R_1111
execute           Bus_In_0000_RLE_false
execute           Bus_In_1111_RLE_false
execute           R_1111
execute           Bus_In_1111
execute           R_0000
execute           Bus_In_0000
execute           R_1111

end unit


!    End of test