!!!!    6    0    1  992022676  Vadb6                                         

! Device           : 75160
! Function         : bus_transceiver oc/tri-state octal
! revision         : B.01.00
! safeguard        : high_out_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

combinatorial

vector cycle 2u
receive  delay 1.9u

assign    VCC       to pins   20
assign    GND       to pins   10

assign    B1        to pins   2
assign    D1        to pins   19
assign    B2        to pins   3
assign    D2        to pins   18
assign    B3        to pins   4
assign    D3        to pins   17
assign    B4        to pins   5
assign    D4        to pins   16
assign    B5        to pins   6
assign    D5        to pins   15
assign    B6        to pins   7
assign    D6        to pins   14
assign    B7        to pins   8
assign    D7        to pins   13
assign    B8        to pins   9
assign    D8        to pins   12

assign    All_B     to pins   2,3,4,5,6,7,8,9
assign    All_D     to pins   19,18,17,16,15,14,13,12

assign    PE          to pins   11
assign    TE          to pins   1

family    TTL

format hexadecimal All_B, All_D

power  VCC, GND

inputs  PE, TE

bidirectional  All_B, All_D
bidirectional  B1, B2, B3, B4, B5, B6, B7, B8 !AT Added for minimum pin test.
bidirectional  D1, D2, D3, D4, D5, D6, D7, D8 !AT Added for minimum pin test.

disable   All_B   with   TE        to     "0"
disable   All_D   with   TE        to     "1"

when  TE    is "0"   inputs   All_B
when  TE    is "0"   outputs  All_D
when  TE    is "1"   inputs   All_D
when  TE    is "1"   outputs  All_B

trace All_D, All_B   to TE, PE
trace D1 to B1
trace B1 to D1
trace D2 to B2
trace B2 to D2
trace D3 to B3
trace B3 to D3
trace D4 to B4
trace B4 to D4
trace D5 to B5
trace B5 to D5
trace D6 to B6
trace B6 to D6
trace D7 to B7
trace B7 to D7
trace D8 to B8
trace B8 to D8

!*********************************************************************
!*********************************************************************

vector    B_to_D_00
     drive  All_B
     receive  All_D
     set  TE            to   "0"
     set  All_B         to   "00"
     set  All_D         to   "00"
end vector

vector    B_to_D_55
     drive  All_B
     receive  All_D
     set  TE            to   "0"
     set  All_B         to   "55"
     set  All_D         to   "55"
end vector

vector    B_to_D_AA
     drive  All_B
     receive  All_D
     set  TE            to   "0"
     set  All_B         to   "AA"
     set  All_D         to   "AA"
end vector

vector    B_to_D_FF
     drive  All_B
     receive  All_D
     set  TE            to   "0"
     set  All_B         to   "FF"
     set  All_D         to   "FF"
end vector

vector    D_to_B_00
     drive  All_D
     receive  All_B
     set  TE            to   "1"
     set  PE            to   "1"
     set  All_D         to   "00"
     set  All_B         to   "00"
end vector

vector    D_to_B_55
     drive  All_D
     receive  All_B
     set  TE            to   "1"
     set  PE            to   "1"
     set  All_D         to   "55"
     set  All_B         to   "55"
end vector

vector    D_to_B_AA
     drive  All_D
     receive  All_B
     set  TE            to   "1"
     set  PE            to   "1"
     set  All_D         to   "AA"
     set  All_B         to   "AA"
end vector

vector    D_to_B_FF
     drive  All_D
     receive  All_B
     set  TE            to   "1"
     set  PE            to   "1"
     set  All_D         to   "FF"
     set  All_B         to   "FF"
end vector



!*****VECTORS FOR DISABLE TESTS*****



vector    B_to_D_00_Disabled
     drive  All_B
     receive  All_D
     set  TE            to   "1"
     set  All_B         to   "00"
     set  All_D         to   "00"
end vector

vector    B_to_D_55_Disabled
     drive  All_B
     receive  All_D
     set  TE            to   "1"
     set  All_B         to   "55"
     set  All_D         to   "55"
end vector

vector    B_to_D_AA_Disabled
     drive  All_B
     receive  All_D
     set  TE            to   "1"
     set  All_B         to   "AA"
     set  All_D         to   "AA"
end vector

vector    B_to_D_FF_Disabled
     drive  All_B
     receive  All_D
     set  TE            to   "1"
     set  All_B         to   "FF"
     set  All_D         to   "FF"
end vector

vector    D_to_B_00_Disabled
     drive  All_D
     receive  All_B
     set  TE            to   "0"
     set  PE            to   "1"
     set  All_D         to   "00"
     set  All_B         to   "00"
end vector

vector    D_to_B_55_Disabled
     drive  All_D
     receive  All_B
     set  TE            to   "0"
     set  PE            to   "1"
     set  All_D         to   "55"
     set  All_B         to   "55"
end vector

vector    D_to_B_AA_Disabled
     drive  All_D
     receive  All_B
     set  TE            to   "0"
     set  PE            to   "1"
     set  All_D         to   "AA"
     set  All_B         to   "AA"
end vector

vector    D_to_B_FF_Disabled
     drive  All_D
     receive  All_B
     set  TE            to   "0"
     set  PE            to   "1"
     set  All_D         to   "FF"
     set  All_B         to   "FF"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    B1_to_D1_0
     drive  B1
     receive  D1
     set  TE            to   "0"
     set  B1            to   "0"
     set  D1            to   "0"
end vector

vector    B1_to_D1_1
     drive  B1
     receive  D1
     set  TE            to   "0"
     set  B1            to   "1"
     set  D1            to   "1"
end vector

vector    B2_to_D2_0
     drive  B2
     receive  D2
     set  TE            to   "0"
     set  B2            to   "0"
     set  D2            to   "0"
end vector

vector    B2_to_D2_1
     drive  B2
     receive  D2
     set  TE            to   "0"
     set  B2            to   "1"
     set  D2            to   "1"
end vector

vector    B3_to_D3_0
     drive  B3
     receive  D3
     set  TE            to   "0"
     set  B3            to   "0"
     set  D3            to   "0"
end vector

vector    B3_to_D3_1
     drive  B3
     receive  D3
     set  TE            to   "0"
     set  B3            to   "1"
     set  D3            to   "1"
end vector

vector    B4_to_D4_0
     drive  B4
     receive  D4
     set  TE            to   "0"
     set  B4            to   "0"
     set  D4            to   "0"
end vector

vector    B4_to_D4_1
     drive  B4
     receive  D4
     set  TE            to   "0"
     set  B4            to   "1"
     set  D4            to   "1"
end vector

vector    B5_to_D5_0
     drive  B5
     receive  D5
     set  TE            to   "0"
     set  B5            to   "0"
     set  D5            to   "0"
end vector

vector    B5_to_D5_1
     drive  B5
     receive  D5
     set  TE            to   "0"
     set  B5            to   "1"
     set  D5            to   "1"
end vector

vector    B6_to_D6_0
     drive  B6
     receive  D6
     set  TE            to   "0"
     set  B6            to   "0"
     set  D6            to   "0"
end vector

vector    B6_to_D6_1
     drive  B6
     receive  D6
     set  TE            to   "0"
     set  B6            to   "1"
     set  D6            to   "1"
end vector

vector    B7_to_D7_0
     drive  B7
     receive  D7
     set  TE            to   "0"
     set  B7            to   "0"
     set  D7            to   "0"
end vector

vector    B7_to_D7_1
     drive  B7
     receive  D7
     set  TE            to   "0"
     set  B7            to   "1"
     set  D7            to   "1"
end vector

vector    B8_to_D8_0
     drive  B8
     receive  D8
     set  TE            to   "0"
     set  B8            to   "0"
     set  D8            to   "0"
end vector

vector    B8_to_D8_1
     drive  B8
     receive  D8
     set  TE            to   "0"
     set  B8            to   "1"
     set  D8            to   "1"
end vector

vector    D1_to_B1_0
     drive  D1
     receive  B1
     set  TE            to   "1"
     set  PE            to   "1"
     set  D1            to   "0"
     set  B1            to   "0"
end vector

vector    D1_to_B1_1
     drive  D1
     receive  B1
     set  TE            to   "1"
     set  PE            to   "1"
     set  D1            to   "1"
     set  B1            to   "1"
end vector

vector    D2_to_B2_0
     drive  D2
     receive  B2
     set  TE            to   "1"
     set  PE            to   "1"
     set  D2            to   "0"
     set  B2            to   "0"
end vector

vector    D2_to_B2_1
     drive  D2
     receive  B2
     set  TE            to   "1"
     set  PE            to   "1"
     set  D2            to   "1"
     set  B2            to   "1"
end vector

vector    D3_to_B3_0
     drive  D3
     receive  B3
     set  TE            to   "1"
     set  PE            to   "1"
     set  D3            to   "0"
     set  B3            to   "0"
end vector

vector    D3_to_B3_1
     drive  D3
     receive  B3
     set  TE            to   "1"
     set  PE            to   "1"
     set  D3            to   "1"
     set  B3            to   "1"
end vector

vector    D4_to_B4_0
     drive  D4
     receive  B4
     set  TE            to   "1"
     set  PE            to   "1"
     set  D4            to   "0"
     set  B4            to   "0"
end vector

vector    D4_to_B4_1
     drive  D4
     receive  B4
     set  TE            to   "1"
     set  PE            to   "1"
     set  D4            to   "1"
     set  B4            to   "1"
end vector

vector    D5_to_B5_0
     drive  D5
     receive  B5
     set  TE            to   "1"
     set  PE            to   "1"
     set  D5            to   "0"
     set  B5            to   "0"
end vector

vector    D5_to_B5_1
     drive  D5
     receive  B5
     set  TE            to   "1"
     set  PE            to   "1"
     set  D5            to   "1"
     set  B5            to   "1"
end vector

vector    D6_to_B6_0
     drive  D6
     receive  B6
     set  TE            to   "1"
     set  PE            to   "1"
     set  D6            to   "0"
     set  B6            to   "0"
end vector

vector    D6_to_B6_1
     drive  D6
     receive  B6
     set  TE            to   "1"
     set  PE            to   "1"
     set  D6            to   "1"
     set  B6            to   "1"
end vector

vector    D7_to_B7_0
     drive  D7
     receive  B7
     set  TE            to   "1"
     set  PE            to   "1"
     set  D7            to   "0"
     set  B7            to   "0"
end vector

vector    D7_to_B7_1
     drive  D7
     receive  B7
     set  TE            to   "1"
     set  PE            to   "1"
     set  D7            to   "1"
     set  B7            to   "1"
end vector

vector    D8_to_B8_0
     drive  D8
     receive  B8
     set  TE            to   "1"
     set  PE            to   "1"
     set  D8            to   "0"
     set  B8            to   "0"
end vector

vector    D8_to_B8_1
     drive  D8
     receive  B8
     set  TE            to   "1"
     set  PE            to   "1"
     set  D8            to   "1"
     set  B8            to   "1"
end vector

!*********************************************************************
!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest Drive B1, Receive D1 Test"
     execute   B1_to_D1_0
     execute   B1_to_D1_1
end unit

unit "awaretest Drive B2, Receive D2 Test"
     execute   B2_to_D2_0
     execute   B2_to_D2_1
end unit

unit "awaretest Drive B3, Receive D3 Test"
     execute   B3_to_D3_0
     execute   B3_to_D3_1
end unit

unit "awaretest Drive B4, Receive D4 Test"
     execute   B4_to_D4_0
     execute   B4_to_D4_1
end unit

unit "awaretest Drive B5, Receive D5 Test"
     execute   B5_to_D5_0
     execute   B5_to_D5_1
end unit

unit "awaretest Drive B6, Receive D6 Test"
     execute   B6_to_D6_0
     execute   B6_to_D6_1
end unit

unit "awaretest Drive B7, Receive D7 Test"
     execute   B7_to_D7_0
     execute   B7_to_D7_1
end unit

unit "awaretest Drive B8, Receive D8 Test"
     execute   B8_to_D8_0
     execute   B8_to_D8_1
end unit

unit "awaretest Drive D1, Receive B1 Test"
     execute   D1_to_B1_0
     execute   D1_to_B1_1
end unit

unit "awaretest Drive D2, Receive B2 Test"
     execute   D2_to_B2_0
     execute   D2_to_B2_1
end unit

unit "awaretest Drive D3, Receive B3 Test"
     execute   D3_to_B3_0
     execute   D3_to_B3_1
end unit

unit "awaretest Drive D4, Receive B4 Test"
     execute   D4_to_B4_0
     execute   D4_to_B4_1
end unit

unit "awaretest Drive D5, Receive B5 Test"
     execute   D5_to_B5_0
     execute   D5_to_B5_1
end unit

unit "awaretest Drive D6, Receive B6 Test"
     execute   D6_to_B6_0
     execute   D6_to_B6_1
end unit

unit "awaretest Drive D7, Receive B7 Test"
     execute   D7_to_B7_0
     execute   D7_to_B7_1
end unit

unit "awaretest Drive D8, Receive B8 Test"
     execute   D8_to_B8_0
     execute   D8_to_B8_1
end unit


unit "Drive B, Receive D"
     execute   B_to_D_00
     execute   B_to_D_55
     execute   B_to_D_AA
     execute   B_to_D_FF
end unit

unit "Drive D, Receive B"
     execute   D_to_B_00
     execute   D_to_B_55
     execute   D_to_B_AA
     execute   D_to_B_FF
end unit



!*****TESTS FOR DISABLE **************************



unit disable test "Disable Test for Output D"
     execute   B_to_D_00_Disabled
     execute   B_to_D_55_Disabled
     execute   B_to_D_AA_Disabled
     execute   B_to_D_FF_Disabled
end unit

unit disable test "Disable Test for Output B"
     execute   D_to_B_00_Disabled
     execute   D_to_B_55_Disabled
     execute   D_to_B_AA_Disabled
     execute   D_to_B_FF_Disabled
end unit



!  End of test