High-Speed Digital Design
Learn the essentials of HSD circuit design
Keep up with the complexity of modern electronics
Discover the four considerations to achieve high-speed digital design success using a holistic design approach from concept to simulation, emulation, and compliance.
Learn the new capabilities introduced with PCIe® 6.0 and the key benefits of an end-to-end solution from simulation to protocol test.
Review the technical road that standards body JEDEC has taken to get to DDR5 and other considerations needed to move beyond DDR5.
Explore USB4 technology, architecture, and multi-level signaling.
What is a Chiplet and Why Should You Care
Discover how chiplets enable an open ecosystem of modular components that can be reused and customized.
Featured courses
Explore design courses on standards
Learn the importance of memory channel pre- and post-layout models and how to build and design with them.
Discover how to use an end-to-end workflow to perform an eye measurement.
High-Speed Digital Interfaces Optimization
Acquire new skills to simulate high-speed digital interfaces and explore design choices to improve signal integrity.
Quick Start to DDR5 Memory Design
Get a quick start on the new challenges with DDR5, and strategies for how to build a new design-to-test workflow for DDR5.
DDR Simulation-Based Compliance Tests
Walk through the compliance tests and design exploration with several memory standards, including (LP) DDR and DDR5.
DDR5 Design Workflow Optimization
Acquire the knowledge to reduce DDR5 loss reflection with integrated design automation and analysis software.
Learn to create and use JEDEC IBIS AMI models for dynamic access-random memory (DRAM) drivers and receivers.
Advanced Techniques for USB4 Simulation and Measurement
Review USB4 technology, signal degradation, channel performance, TP3 compliance point, and multi-level signaling.
Discover courses on signal integrity
Discover three ways to optimize signal integrity in your design, and how to fix unexpected differential impedance, SDD11, and SDD21.
Design a Robust Workflow for Signal Integrity
Walkthrough the mechanisms that affect signal integrity and learn practical tips for troubleshooting designs.
Find and Solve Signal Integrity Issues
Learn how to identify signal integrity issues and get techniques that will help you open your digital channel's eyes.
Explore courses on power integrity
Learn conducted electromagnetic interference (CEMI), standards, and how to set up and run simulations.
Capacitor Selection, Placement, and Optimization
Use EM simulators to select the correct capacitors and optimize the placement for quiet power distribution.
Power Integrity Simulation Workflow
Learn how to use an end-to-end workflow that is ideal for solving the next generation of low voltage, high-current power delivery designs.
Power Distribution Network Design
Discover a comprehensive power integrity workflow to design for flat impedance and identify the root cause of ringing on power rails.
Power Integrity Simulation & Measurement Skills
Apply digital twins to simulate designs and use advanced oscilloscopes to measure power integrity signals.
HSD: Go deeper
Learn more with a deeper dive into signal and power integrity with a curated selection of advanced topics.
Related use cases
-
![How to Optimize 800G Optical Transceiver Manufacturing Tests]()
How to Optimize 800G Optical Transceiver Manufacturing Tests
Manufacturing testing optical data center transceivers requires efficient analysis of TDECQ measurements. Learn how parallel data acquisition and analysis increases throughput to save cost of high-volume testing.
Learn more
-
![How to Test USB4 Version 2.0 Receiver Compliance]()
How to Test USB4 Version 2.0 Receiver Compliance
USB4 Version 2.0 receiver testing requires precise stress signal calibration, consistently repeatable pattern generation, and bit error rate measurements. Learn how to perform a USB4 Version 2.0 receiver compliance test using a bit error ratio tester (BERT), a high-bandwidth oscilloscope, USB receiver test application software, and the USB-IF SigTest utility.
Learn more
-
![How to Test for HDMI Physical Layer Source Compliance]()
How to Test for HDMI Physical Layer Source Compliance
HDMI source compliance testing requires thorough verification to ensure HDMI devices meet compliance test specifications (CTS). Learn how to test HDMI physical layer source compliance by measuring signal integrity, timing, and other critical parameters.
Learn more
Dive into more insights and carefully compiled resources on high-speed digital design
