Optimize Power Distribution Networks for Flat Impedance
应用文章
It takes only one rogue wave to kill a power distribution network in high-speed digital designs. Flat impedance optimization before layout lowers the risk.
Power integrity (PI) engineers use target impedance to design power delivery across a broad frequency range. Target impedance is a simple estimate using the maximum allowed ripple divided by the maximum expected current step load. For example, in a field programmable gate array (FPGA) where the max ripple is 60 mV and the max current step load is 5 A, the target impedance (Z) is 12 mΩ.
Achieving this target impedance across a broad frequency range requires a power supply for the low frequencies and decoupling capacitors for the higher frequencies. The challenge is to get the best performance at the lowest cost. Flat impedance design makes that possible. A power distribution network (PDN) designed for flat impedance uses the minimum number of capacitors to achieve a target impedance while avoiding high Q resonances that can cause rogue voltage waves. Reducing part count has the added benefit of higher reliability with fewer solder joints.