224 Gb/s SerDes Conformance Demo

In this video, John Calvin, a high-speed serial data planner for Keysight Technologies, presents a demonstration of the 224 Gb/s SERDES transmitter conformance test setup. Calvin begins by introducing the context of 1.6 terabit technology and the unique testing challenges associated with 200 gigabits per second (Gb/s) signaling. He highlights the capabilities of the Infiniium UXR-series oscilloscope in validating 200 Gb/s electrical interfaces.

One of the primary advantages of the UXR oscilloscope is its 80 GHz bandwidth, which is essential for achieving the reference receivers and technical attributes required for effective testing. Calvin identifies key challenges in the 224 Gb/s electrical validation field, including significant channel loss, which can range from 23 to 33 dB depending on the electrical configuration. This loss equates to a substantial 50:1 signal loss ratio. Additionally, the signal-to-noise ratio presents real technical difficulties in compensating for and equalizing these signals to perform basic measurements.

Another critical aspect of this validation process is clock recovery. Clock recovery involves extracting the encoded clock from the data stream for measurement purposes. The UXR oscilloscope's real-time instrument offers an oversample architecture, acquiring signals above Nyquist at 256 GSa/s. This capability allows clock recovery through digital signal processing (DSP), providing greater flexibility compared to traditional instruments that require physical hardware for clock recovery. This software-based approach enables testing at various rates as long as Nyquist rules are observed.

Calvin further explains the instrument's ability to perform jitter decomposition, showcasing a J4U calculation with approximately 84 milliUI of jitter in the current configuration. This configuration is referred to as a TP0V, a validation test point closest to the silicon before passing through the test fixture. This test point is crucial for assessing the initial performance of the silicon.

In addition to jitter decomposition, the video highlights the importance of measuring Signal to Noise Distortion Ratio (SNDR), a key indicator of electrical design health. SNDR targets vary depending on the channel structure, with allowances decreasing as signal loss increases. Calvin demonstrates SNDR measurements in the range of 30-31.5 dB, aligning with IEEE and OIF-CEI specifications for the test point.

The demo also includes rendering eye diagrams and showcasing partial response-based equalization techniques. These advanced equalization methods represent a significant improvement over traditional techniques, allowing for better signal recovery and analysis in line with emerging specifications.