U4301B PCI Express® 3.0 Analyzer Module

技术资料

Keysight U4301B

PCI Express® 3.0 Analyzer Module

Data Sheet

PCIe® 3.1 support with L1 substate analysis
Separate reference clock with SSC (SRIS) support
Probing solution for all popular interfaces
CEM slot through x1 through x16
U.2 (SFF-8639) single and dual link
M.2 mini PCIe connection
Detailed LTSSM equalization analysis
NVMe protocol analysis
AHCI protocol analysis

Introduction

The Keysight Technologies, Inc. high speed U4301B PCI Express 3.0 analyzer module is a protocol analyzer supporting all PCI Express® applications from Gen1 through Gen3, at speeds, including 2.5 GT/s (Gen1) and 5.0 GT/s (Gen2) through PCIe 8 GT/s (Gen3), and with link widths from x1 to x16. The U4301B analyzer captures and decodes PCI Express data and displays it in a packet viewer window.

The U4301B analyzer is a blade that installs into an AXIe two-slot M9502A or five-slot M9505A.

Probing is provided by the U4321A solid-slot interposer probe, U4324A flying lead solder down probe, or the U4322A mid-bus probe based on Keysight’s equalization snoop probe (ESP) technology.

Gain insight into the equalization process and all of the state transitions with views that can be customized to meet your requirements. The analyzer ’s LTSSM overview can pinpoint specific training sequence issues through easy-to-interpret analysis results.

Keysight’s transactional decoder includes a transactional viewer that allows the designer to select transactional queues and performance information from the analyzer’s NVMe transaction overview pane. This organizes the transactions by direction or by queue to follow the data flow across the interface, with one-click control. Individual PRP (Physical Region Page) lists contain all of the key information of the NVMe queues, allowing designers to quickly review and validate the data flows over the PCIe connections.

The performance analysis package includes the real data throughput calculations, with response-time measurement of the PCIe data flow. It allows designers to measure and understand throughput performance, PCIe response times, and other operational measurements that provide the insight needed to optimize device performance.

Complementary PCIe stimulus and response testing of the PCIe system is accomplished with the addition of the U4305B PCIe Gen3 exerciser.

Keysight solutions for PCIe Gen1 to Gen3 analysis and emulation

PCIe Gen1 (2.5 GT/s), Gen2 (5 GT/s), and Gen3 (8 GT/s) support
Auto link configuration for up to x16 link width (auto speed, auto link width, auto link reversal, auto polarity)
LTSSM analysis with equalization reporting
Power state analysis includes L1 substate operation
Flow control credit and performance analysis
PCIe, NVMe, AHCI, and configuration space decoding and analysis
Compact AXIe modular system configuration

Overview (Continued)

Analysis and debug

Supports Gen1 through Gen3, x1 through x16 link width
8 GB of capture buffer per module
Non-intrusive probing that leverages ESP technology

Industry leading probes

Mid-bus probe supports x1 to x16 unidirectional, or x1 to x8 bidirectional
Solid slot interposer supports x1 to x16 unidirectional or bidirectional
Flying lead solder down probe supports x1 and x2 bidirectional capability on a single probe. Other standard lane width configuration support is x4, x8, and x16
M.2 interposer supports testing of M/B-M PCIe solid state drives (SSDs)
SFF-8639 interposers can be used with solid state drives (SSDs) with either single or dual link support

Stimulus and test U4305B exerciser

Support for Gen1 through Gen3 and link widths of x1 through x16
Link testing from x1 through x16 using automated LTSSM exerciser
PCIe, MR-IOV, and SR-IOV stimulus response testing
NVMe root complex emulation for test and verification of NVMe devices
Protocol test card (PTC) to measure PCIe Gen3 DUT port and system BIOS specification compliance as defined by the PCI-SIG® standards