DesignCon 2025

Keysight Chiplet PHY Designer is an advanced design tool that analyzes and optimizes chiplet-based systems, focusing on the UCIe and Bunch of Wires (BoW) standards. This cutting-edge tool empowers designers to gain in-depth insights into their designs, identify potential bottlenecks, and implement optimizations that enhance system integration and overall performance in chiplet-based architectures.

Keysight PCIe® test solutions cover design and protocol testing. Demo highlights include the P557xA protocol analyzer and exerciser products and physical layer test tools such as the UXR-Series oscilloscope and M8050A bit error rate testing (BERT) platform.

Using the Keysight UXR-Series oscilloscope and D90203DJC electrical transmitter compliance test software, we will demonstrate how to efficiently test P802.3dj Ethernet (1.6 Tbps).

The next-generation interconnect architecture for high-performance artificial intelligence (AI) clusters is advancing to 448 Gbps interfaces for 3.2Tbps systems sooner than expected. Keysight will showcase its M8199B arbitrary waveform generator and other key tools enabling this technology.

Physical Layer Test System (PLTS) 2025 is advanced signal integrity application software that streamlines the calibration, measurement, and post-processing of vector network analyzer and time domain reflectometer data. It accelerates time to market for high-speed digital interconnects such as backplanes, printed circuit boards, cables, and connectors — critical internet infrastructure components that demand high-bandwidth design.

Keysight will showcase comprehensive USB4 solutions for compliance and validation using the UXR-Series oscilloscope and the M8040A / M8050A BERT platform.

The Keysight Interconnect and Network Performance Tester 800GE, the benchtop PAM4 Ethernet test system, and the AI Data Center Test Builder measure optical and electrical interconnect BER and perform forward error correction — essential for high-data-volume AI applications.

Next-generation memory designs require lower noise and reduced loading to reflect design performance accurately. This demo showcases the Keysight D9060LDDC LPDDR6 test application to validate the capabilities of next-generation LPDDR6 memory designs.